diff --git a/apps/uefi/Bsa.inf b/apps/uefi/Bsa.inf
index 065ef1f7..123bbadf 100644
--- a/apps/uefi/Bsa.inf
+++ b/apps/uefi/Bsa.inf
@@ -96,6 +96,7 @@
../../test_pool/memory_map/m001.c
../../test_pool/memory_map/m002.c
../../test_pool/memory_map/m003.c
+ ../../test_pool/memory_map/m004.c
../../test_pool/power_wakeup/u001.c
../../test_pool/power_wakeup/u002.c
../../test_pool/power_wakeup/u003.c
diff --git a/apps/uefi/Mem.inf b/apps/uefi/Mem.inf
index aa8a5e07..47eedb63 100644
--- a/apps/uefi/Mem.inf
+++ b/apps/uefi/Mem.inf
@@ -92,6 +92,7 @@
../../test_pool/peripherals/d005.c
../../test_pool/memory_map/m002.c
../../test_pool/memory_map/m003.c
+ ../../test_pool/memory_map/m004.c
../../test_pool/power_wakeup/u001.c
../../test_pool/power_wakeup/u002.c
../../test_pool/power_wakeup/u003.c
diff --git a/apps/uefi/Sbsa.inf b/apps/uefi/Sbsa.inf
index 9274b607..885d738a 100644
--- a/apps/uefi/Sbsa.inf
+++ b/apps/uefi/Sbsa.inf
@@ -99,6 +99,7 @@
../../test_pool/memory_map/m001.c
../../test_pool/memory_map/m002.c
../../test_pool/memory_map/m003.c
+ ../../test_pool/memory_map/m004.c
../../test_pool/power_wakeup/u001.c
../../test_pool/power_wakeup/u002.c
../../test_pool/power_wakeup/u003.c
diff --git a/apps/uefi/Vbsa.inf b/apps/uefi/Vbsa.inf
index 44a04432..4ce9b482 100644
--- a/apps/uefi/Vbsa.inf
+++ b/apps/uefi/Vbsa.inf
@@ -98,6 +98,7 @@
../../test_pool/memory_map/m001.c
../../test_pool/memory_map/m002.c
../../test_pool/memory_map/m003.c
+ ../../test_pool/memory_map/m004.c
../../test_pool/power_wakeup/u001.c
../../test_pool/power_wakeup/u002.c
../../test_pool/power_wakeup/u003.c
diff --git a/apps/uefi/pc_bsa.inf b/apps/uefi/pc_bsa.inf
index 72180e1a..0d2b9cd0 100644
--- a/apps/uefi/pc_bsa.inf
+++ b/apps/uefi/pc_bsa.inf
@@ -99,6 +99,7 @@
../../test_pool/memory_map/m001.c
../../test_pool/memory_map/m002.c
../../test_pool/memory_map/m003.c
+ ../../test_pool/memory_map/m004.c
../../test_pool/power_wakeup/u001.c
../../test_pool/power_wakeup/u002.c
../../test_pool/power_wakeup/u003.c
diff --git a/apps/uefi/xbsa_acpi.inf b/apps/uefi/xbsa_acpi.inf
index 0a76177e..d6371b70 100644
--- a/apps/uefi/xbsa_acpi.inf
+++ b/apps/uefi/xbsa_acpi.inf
@@ -95,6 +95,7 @@
../../test_pool/memory_map/m001.c
../../test_pool/memory_map/m002.c
../../test_pool/memory_map/m003.c
+ ../../test_pool/memory_map/m004.c
../../test_pool/power_wakeup/u001.c
../../test_pool/power_wakeup/u002.c
../../test_pool/power_wakeup/u003.c
diff --git a/docs/bsa/arm_bsa_testcase_checklist.md b/docs/bsa/arm_bsa_testcase_checklist.md
index 801f1a02..b490d755 100644
--- a/docs/bsa/arm_bsa_testcase_checklist.md
+++ b/docs/bsa/arm_bsa_testcase_checklist.md
@@ -1263,7 +1263,7 @@ The checklist provides information about:
| PCI_IN_19 |
830 |
- Check Cmd Reg memory space enable |
+ Check Command,BIST,and Hdr Cap registers |
Yes |
Yes |
No |
@@ -3260,7 +3260,7 @@ The checklist provides information about:
| PCI_IN_19 |
830 |
- Check Cmd Reg memory space enable |
+ Check Command,BIST,and Hdr Cap registers |
Yes |
Yes |
No |
diff --git a/docs/sbsa/arm_sbsa_testcase_checklist.md b/docs/sbsa/arm_sbsa_testcase_checklist.md
index d91c2784..e7cdfaeb 100644
--- a/docs/sbsa/arm_sbsa_testcase_checklist.md
+++ b/docs/sbsa/arm_sbsa_testcase_checklist.md
@@ -1918,7 +1918,7 @@ The checklist provides information about:
| PCI_IN_19 |
|
- Check Cmd Reg memory space enable |
+ Check Command,BIST,and Hdr Cap registers |
Yes |
Yes |
No |
diff --git a/docs/vbsa/arm_vbsa_testcase_checklist.md b/docs/vbsa/arm_vbsa_testcase_checklist.md
index 50ba05a7..30626217 100644
--- a/docs/vbsa/arm_vbsa_testcase_checklist.md
+++ b/docs/vbsa/arm_vbsa_testcase_checklist.md
@@ -835,7 +835,7 @@ The checklist provides information about:
| PCI_IN_19 |
830 |
- Check Cmd Reg memory space enable |
+ Check Command,BIST,and Hdr Cap registers |
✅ |
❌ |
|
diff --git a/pal/uefi_acpi/src/pal_pcie.c b/pal/uefi_acpi/src/pal_pcie.c
index d6f1101d..c20e7430 100644
--- a/pal/uefi_acpi/src/pal_pcie.c
+++ b/pal/uefi_acpi/src/pal_pcie.c
@@ -618,5 +618,71 @@ pal_pcie_is_device_behind_smmu(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
UINT32
pal_pcie_is_devicedma_64bit(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
{
- return 0;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *Pci;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Seg, Bus, Dev, Func;
+ UINT32 Index;
+ UINT64 Supported;
+ UINT64 Current;
+ INT8 Is64Bit = 0;
+
+ Status = gBS->LocateHandleBuffer(ByProtocol, &gEfiPciIoProtocolGuid, NULL,
+ &HandleCount, &HandleBuffer);
+ if (EFI_ERROR(Status)) {
+ pal_print_msg(ACS_PRINT_ERR, " No PCI devices found in the system\n");
+ return 0;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol(HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID **)&Pci);
+ if (EFI_ERROR(Status))
+ continue;
+
+ Pci->GetLocation(Pci, &Seg, &Bus, &Dev, &Func);
+ if (Seg != seg || Bus != bus || Dev != dev || Func != fn)
+ continue;
+
+ Status = Pci->Attributes(Pci, EfiPciIoAttributeOperationSupported, 0, &Supported);
+ if (!EFI_ERROR(Status) && (Supported & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE)) {
+
+ /* Prefer reporting only if DAC is actually enabled */
+ Status = Pci->Attributes(Pci, EfiPciIoAttributeOperationGet, 0, &Current);
+ if (!EFI_ERROR(Status) && (Current & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE)) {
+ Is64Bit = 1;
+ } else {
+ /*
+ * Try enabling DAC to see if firmware/platform allows it.
+ * Do not treat failure as fatal; we simply report lack of 64-bit DMA.
+ */
+ Status = Pci->Attributes(Pci, EfiPciIoAttributeOperationEnable,
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE, NULL);
+ if (!EFI_ERROR(Status)) {
+ Status = Pci->Attributes(Pci, EfiPciIoAttributeOperationGet, 0, &Current);
+ if (!EFI_ERROR(Status) && (Current & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE))
+ Is64Bit = 1;
+ }
+ }
+ }
+
+ break;
+ }
+ pal_mem_free(HandleBuffer);
+ return Is64Bit;
+}
+
+/**
+ @brief Placeholder for UEFI
+
+ @param seg PCI segment number
+ @param bus PCI bus address
+ @param dev PCI device address
+ @param fn PCI function number
+
+ @retval Return 1
+**/
+UINT32 pal_pcie_device_driver_present(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn)
+{
+ return 1;
}
diff --git a/pal/uefi_acpi/src/pal_peripherals.c b/pal/uefi_acpi/src/pal_peripherals.c
index fb00e569..9bd8a5d5 100644
--- a/pal/uefi_acpi/src/pal_peripherals.c
+++ b/pal/uefi_acpi/src/pal_peripherals.c
@@ -24,7 +24,9 @@
#include
#include
+#include
#include "Include/IndustryStandard/Acpi61.h"
+#include "Include/IndustryStandard/Pci22.h"
#include "Include/IndustryStandard/SerialPortConsoleRedirectionTable.h"
#include "pal_uefi.h"
@@ -41,6 +43,144 @@ UINT32 spcr_baudrate_id[] = {0, 0, 0, 9600, 19200, 0, 57600, 115200};
UINT64
pal_get_spcr_ptr();
+STATIC
+BOOLEAN
+pal_peripheral_is_duplicate(PERIPHERAL_INFO_BLOCK *start,
+ PERIPHERAL_INFO_BLOCK *current,
+ UINT32 bdf)
+{
+ PERIPHERAL_INFO_BLOCK *iter = start;
+
+ while (iter < current) {
+ if ((iter->bdf == bdf) && (bdf != 0))
+ return TRUE;
+ iter++;
+ }
+
+ return FALSE;
+}
+
+STATIC
+UINT64
+pal_peripheral_get_bar_value(UINT32 *bar, UINT32 bar_index, UINT32 max_bars)
+{
+ UINT64 bar_value;
+
+ if (bar_index >= max_bars)
+ return 0;
+
+ bar_value = bar[bar_index];
+
+ if ((((bar_value) >> BAR_MDT_SHIFT) & BAR_MDT_MASK) == BITS_64) {
+ if ((bar_index + 1) < max_bars) {
+ bar_value = bar[bar_index + 1];
+ bar_value = (bar_value << 32) | bar[bar_index];
+ }
+ }
+
+ return bar_value;
+}
+
+STATIC
+VOID
+pal_peripheral_add_all_pci(PERIPHERAL_INFO_TABLE *peripheralInfoTable,
+ PERIPHERAL_INFO_BLOCK **per_info)
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *Pci;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+ UINTN Seg, Bus, Dev, Func;
+ UINT32 bar_index;
+ UINT32 bar_count;
+ UINT32 DeviceBdf;
+ UINT32 *bars;
+ UINT32 class_code;
+ PCI_TYPE_GENERIC PciHeader;
+ PERIPHERAL_INFO_BLOCK *info = *per_info;
+ PERIPHERAL_INFO_BLOCK *start = peripheralInfoTable->info;
+
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL,
+ &HandleCount, &HandleBuffer);
+ if (EFI_ERROR (Status)) {
+ pal_print_msg(ACS_PRINT_ERR, " No PCI devices found while populating peripheral table\n");
+ return;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID **)&Pci);
+ if (EFI_ERROR (Status))
+ continue;
+
+ Status = Pci->GetLocation (Pci, &Seg, &Bus, &Dev, &Func);
+ if (EFI_ERROR (Status))
+ continue;
+
+ DeviceBdf = (UINT32)PCIE_CREATE_BDF(Seg, Bus, Dev, Func);
+
+ if (pal_peripheral_is_duplicate(start, info, DeviceBdf))
+ continue;
+
+ Status = Pci->Pci.Read (Pci, EfiPciIoWidthUint32, 0,
+ sizeof (PciHeader)/sizeof (UINT32), &PciHeader);
+ if (EFI_ERROR (Status))
+ continue;
+
+ /* We only want endpoint functions (header type = device) */
+ if ((PciHeader.Device.Hdr.HeaderType & HEADER_LAYOUT_CODE) != HEADER_TYPE_DEVICE)
+ continue;
+
+ /* Skip bridges and cardbus controllers, we only want endpoint functions */
+ if (IS_PCI_BRIDGE(&(PciHeader.Bridge)) || IS_CARDBUS_BRIDGE(&(PciHeader.Bridge)))
+ continue;
+
+ bars = PciHeader.Device.Device.Bar;
+ bar_count = TYPE0_MAX_BARS;
+ class_code = ((PciHeader.Device.Hdr.ClassCode[2] << 16) |
+ (PciHeader.Device.Hdr.ClassCode[1] << 8) |
+ PciHeader.Device.Hdr.ClassCode[0]);
+
+ /* Skip all bridge class devices (host bridge, PCI-PCI bridge, etc.) */
+ if ((class_code >> 16) == 0x06)
+ continue;
+
+ info->type = PERIPHERAL_TYPE_OTHER;
+ info->bdf = DeviceBdf;
+ info->platform_type = PLATFORM_TYPE_ACPI;
+ info->base0 = 0;
+ info->base1 = 0;
+ info->width = 0;
+ info->irq = 0;
+ info->flags = 0;
+ info->msi = 0;
+ info->msix = 0;
+ info->max_pasids = 0;
+ info->baud_rate = 0;
+ info->interface_type = 0;
+
+ for (bar_index = 0; bar_index < bar_count; bar_index++) {
+ UINT64 bar_value = pal_peripheral_get_bar_value(bars, bar_index, bar_count);
+
+ if (bar_value != 0) {
+ if (info->base0 == 0)
+ info->base0 = bar_value;
+ else if (info->base1 == 0)
+ info->base1 = bar_value;
+ }
+
+ if ((((bars[bar_index]) >> BAR_MDT_SHIFT) & BAR_MDT_MASK) == BITS_64)
+ bar_index++;
+ }
+
+ peripheralInfoTable->header.num_all++;
+ info++;
+ }
+
+ pal_mem_free(HandleBuffer);
+ *per_info = info;
+}
+
/**
@brief This API fills in the PERIPHERAL_INFO_TABLE with information about peripherals
in the system. This is achieved by parsing the ACPI - SPCR table and PCIe config space.
@@ -164,6 +304,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
per_info++;
}
+ pal_peripheral_add_all_pci(peripheralInfoTable, &per_info);
per_info->type = 0xFF; //indicate end of table
}
diff --git a/pal/uefi_dt/src/pal_pcie.c b/pal/uefi_dt/src/pal_pcie.c
index 89fd1bf9..de822003 100644
--- a/pal/uefi_dt/src/pal_pcie.c
+++ b/pal/uefi_dt/src/pal_pcie.c
@@ -543,9 +543,59 @@ pal_pcie_is_onchip_peripheral(UINT32 bdf)
UINT32
pal_pcie_is_devicedma_64bit(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
{
- return 0;
-}
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *Pci;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Seg, Bus, Dev, Func;
+ UINT32 Index;
+ UINT64 Supported;
+ UINT64 Current;
+ INT8 Is64Bit = 0;
+
+ Status = gBS->LocateHandleBuffer(ByProtocol, &gEfiPciIoProtocolGuid, NULL,
+ &HandleCount, &HandleBuffer);
+ if (EFI_ERROR(Status)) {
+ pal_print_msg(ACS_PRINT_ERR, " No PCI devices found in the system\n");
+ return 0;
+ }
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol(HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID **)&Pci);
+ if (EFI_ERROR(Status))
+ continue;
+
+ Pci->GetLocation(Pci, &Seg, &Bus, &Dev, &Func);
+ if (Seg != seg || Bus != bus || Dev != dev || Func != fn)
+ continue;
+
+ Status = Pci->Attributes(Pci, EfiPciIoAttributeOperationSupported, 0, &Supported);
+ if (!EFI_ERROR(Status) && (Supported & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE)) {
+
+ /* Prefer reporting only if DAC is actually enabled */
+ Status = Pci->Attributes(Pci, EfiPciIoAttributeOperationGet, 0, &Current);
+ if (!EFI_ERROR(Status) && (Current & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE)) {
+ Is64Bit = 1;
+ } else {
+ /*
+ * Try enabling DAC to see if firmware/platform allows it.
+ * Do not treat failure as fatal; we simply report lack of 64-bit DMA.
+ */
+ Status = Pci->Attributes(Pci, EfiPciIoAttributeOperationEnable,
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE, NULL);
+ if (!EFI_ERROR(Status)) {
+ Status = Pci->Attributes(Pci, EfiPciIoAttributeOperationGet, 0, &Current);
+ if (!EFI_ERROR(Status) && (Current & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE))
+ Is64Bit = 1;
+ }
+ }
+ }
+
+ break;
+ }
+ pal_mem_free(HandleBuffer);
+ return Is64Bit;
+}
/**
@brief Checks the discovered PCIe hierarchy is matching with the
topology described in info table.
@@ -702,3 +752,18 @@ pal_pcie_mem_get_offset(UINT32 bdf, PCIE_MEM_TYPE_INFO_e mem_type)
return MEM_OFFSET_SMALL;
}
+
+/**
+ @brief Placeholder for UEFI
+
+ @param seg PCI segment number
+ @param bus PCI bus address
+ @param dev PCI device address
+ @param fn PCI function number
+
+ @retval return 1
+**/
+UINT32 pal_pcie_device_driver_present(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn)
+{
+ return 1;
+}
diff --git a/pal/uefi_dt/src/pal_peripherals.c b/pal/uefi_dt/src/pal_peripherals.c
index ce02ac75..1d0ac4e9 100644
--- a/pal/uefi_dt/src/pal_peripherals.c
+++ b/pal/uefi_dt/src/pal_peripherals.c
@@ -26,7 +26,9 @@
#include
#include
+#include
#include "Include/IndustryStandard/Acpi61.h"
+#include "Include/IndustryStandard/Pci22.h"
#include "Include/IndustryStandard/SerialPortConsoleRedirectionTable.h"
#include "platform_override.h"
@@ -65,6 +67,132 @@ static char uart_dt_compatible[][UART_COMPATIBLE_STR_LEN] = {
"ns8250",
};
+STATIC
+BOOLEAN
+pal_peripheral_is_duplicate(PERIPHERAL_INFO_BLOCK *start,
+ PERIPHERAL_INFO_BLOCK *current,
+ UINT32 bdf)
+{
+ PERIPHERAL_INFO_BLOCK *iter = start;
+
+ while (iter < current) {
+ if ((iter->bdf == bdf) && (bdf != 0))
+ return TRUE;
+ iter++;
+ }
+
+ return FALSE;
+}
+
+STATIC
+UINT64
+pal_peripheral_get_bar_value(UINT32 *bar, UINT32 bar_index, UINT32 max_bars)
+{
+ UINT64 bar_value;
+
+ if (bar_index >= max_bars)
+ return 0;
+
+ bar_value = bar[bar_index];
+
+ if ((((bar_value) >> BAR_MDT_SHIFT) & BAR_MDT_MASK) == BITS_64) {
+ if ((bar_index + 1) < max_bars) {
+ bar_value = bar[bar_index + 1];
+ bar_value = (bar_value << 32) | bar[bar_index];
+ }
+ }
+
+ return bar_value;
+}
+
+STATIC
+VOID
+pal_peripheral_add_all_pci(PERIPHERAL_INFO_TABLE *peripheralInfoTable,
+ PERIPHERAL_INFO_BLOCK **per_info)
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *Pci;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+ UINTN Seg, Bus, Dev, Func;
+ UINT32 bar_index;
+ UINT32 bar_count;
+ UINT32 DeviceBdf;
+ UINT32 *bars;
+ PCI_TYPE_GENERIC PciHeader;
+ PERIPHERAL_INFO_BLOCK *info = *per_info;
+ PERIPHERAL_INFO_BLOCK *start = peripheralInfoTable->info;
+
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL,
+ &HandleCount, &HandleBuffer);
+ if (EFI_ERROR (Status)) {
+ pal_print_msg(ACS_PRINT_ERR, " No PCI devices found while populating peripheral table\n");
+ return;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID **)&Pci);
+ if (EFI_ERROR (Status))
+ continue;
+
+ Status = Pci->GetLocation (Pci, &Seg, &Bus, &Dev, &Func);
+ if (EFI_ERROR (Status))
+ continue;
+
+ DeviceBdf = (UINT32)PCIE_CREATE_BDF(Seg, Bus, Dev, Func);
+
+ if (pal_peripheral_is_duplicate(start, info, DeviceBdf))
+ continue;
+
+ Status = Pci->Pci.Read (Pci, EfiPciIoWidthUint32, 0,
+ sizeof (PciHeader)/sizeof (UINT32), &PciHeader);
+ if (EFI_ERROR (Status))
+ continue;
+
+ bars = PciHeader.Device.Device.Bar;
+ bar_count = TYPE0_MAX_BARS;
+ if (IS_PCI_BRIDGE(&(PciHeader.Bridge)) || IS_CARDBUS_BRIDGE(&(PciHeader.Bridge))) {
+ bars = PciHeader.Bridge.Bridge.Bar;
+ bar_count = TYPE1_MAX_BARS;
+ }
+
+ info->type = PERIPHERAL_TYPE_OTHER;
+ info->bdf = DeviceBdf;
+ info->platform_type = PLATFORM_TYPE_DT;
+ info->base0 = 0;
+ info->base1 = 0;
+ info->width = 0;
+ info->irq = 0;
+ info->flags = 0;
+ info->msi = 0;
+ info->msix = 0;
+ info->max_pasids = 0;
+ info->baud_rate = 0;
+ info->interface_type = 0;
+
+ for (bar_index = 0; bar_index < bar_count; bar_index++) {
+ UINT64 bar_value = pal_peripheral_get_bar_value(bars, bar_index, bar_count);
+
+ if (bar_value != 0) {
+ if (info->base0 == 0)
+ info->base0 = bar_value;
+ else if (info->base1 == 0)
+ info->base1 = bar_value;
+ }
+
+ if ((((bars[bar_index]) >> BAR_MDT_SHIFT) & BAR_MDT_MASK) == BITS_64)
+ bar_index++;
+ }
+
+ peripheralInfoTable->header.num_all++;
+ info++;
+ }
+
+ pal_mem_free(HandleBuffer);
+ *per_info = info;
+}
+
/**
@brief This API fills in the PERIPHERAL_INFO_TABLE with information about USB
in the system. This is achieved by parsing the DT.
@@ -737,6 +865,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
per_info++;
}
+ pal_peripheral_add_all_pci(peripheralInfoTable, &per_info);
per_info->type = 0xFF; //indicate end of table
dt_dump_peripheral_table(peripheralInfoTable);
}
diff --git a/test_pool/memory_map/m004.c b/test_pool/memory_map/m004.c
index a613b12d..860405b9 100644
--- a/test_pool/memory_map/m004.c
+++ b/test_pool/memory_map/m004.c
@@ -126,6 +126,8 @@ payload_check_if_non_dma_dev_behind_smmu (void)
{
uint32_t i, fail_cnt = 0;
bool test_run = 0;
+ uint32_t bdf;
+ uint32_t smmu_index;
uint32_t index = val_pe_get_index_mpid (val_pe_get_mpid());
pcie_bdf_list_t *pcie_peripherals_bdf_list = val_pcie_get_pcie_peripheral_bdf_list();
@@ -136,19 +138,20 @@ payload_check_if_non_dma_dev_behind_smmu (void)
val_set_status(index, RESULT_WARNING(1));
return;
}
-
/* Check if a device is capable of accessing non secure address */
for (i = 0; i < pcie_peripherals_bdf_list->count; i++) {
/* Test is valid for devices which can't DMA and fail if such
device not behind a SMMU */
if (!(val_pcie_is_devicedma_64bit(pcie_peripherals_bdf_list->dev_bdfs[i]))) {
+ bdf = pcie_peripherals_bdf_list->dev_bdfs[i];
/* Flag if test is run, since check is conditional on availability of
non DMA devices */
test_run = 1;
/* Mark has fail if non DMA device not behind SMMU */
- if (!(val_pcie_is_device_behind_smmu(pcie_peripherals_bdf_list->dev_bdfs[i]))) {
- val_print(DEBUG, "\n Failed for BDF = 0x%x",
- pcie_peripherals_bdf_list->dev_bdfs[i]);
+ smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(bdf),
+ PCIE_CREATE_BDF_PACKED(bdf));
+ if (smmu_index == ACS_INVALID_INDEX) {
+ val_print(DEBUG, "\n Failed for BDF = 0x%x", bdf);
fail_cnt++;
}
}
diff --git a/test_pool/memory_map/m005.c b/test_pool/memory_map/m005.c
index 5d5f463c..c28dbf33 100644
--- a/test_pool/memory_map/m005.c
+++ b/test_pool/memory_map/m005.c
@@ -88,7 +88,7 @@ static void payload_check_peripheral_addr_64kb_apart(void)
uint32_t peri_index, peri_index1;
uint64_t peri_count, addr_diff;
uint64_t peri_addr1, peri_addr2;
- uint32_t fail_cnt = 0;
+ uint32_t warn_cnt = 0;
pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
peri_count = val_peripheral_get_info(NUM_ALL, 0);
@@ -116,15 +116,17 @@ static void payload_check_peripheral_addr_64kb_apart(void)
peri_addr1 - peri_addr2 : peri_addr2 - peri_addr1;
if (addr_diff < MEM_SIZE_64KB) {
- val_print(ERROR,
+ val_print(WARN,
"\n Peripheral base addresses isn't atleast 64Kb apart %llx", addr_diff);
- fail_cnt++;
+ warn_cnt++;
}
}
}
- if (fail_cnt) {
- val_set_status(pe_index, RESULT_FAIL(01));
+ if (warn_cnt) {
+ val_print(WARN,
+ "\n Make sure peripherals assigned to different VMs are 64kb apart");
+ val_set_status(pe_index, RESULT_WARNING(01));
} else {
val_set_status(pe_index, RESULT_PASS);
}
diff --git a/val/src/rule_metadata.c b/val/src/rule_metadata.c
index 9c60fcb0..04b02831 100644
--- a/val/src/rule_metadata.c
+++ b/val/src/rule_metadata.c
@@ -881,7 +881,7 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
.test_entry_id = M007_ENTRY,
.module_id = MEM_MAP,
.rule_desc = "Check NS non-64b DMA devices are behind SMMU",
- .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_LINUX,
+ .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI | PLATFORM_LINUX,
.flag = BASE_RULE,
.test_num = ACS_MEMORY_MAP_TEST_NUM_BASE + 7,
},
@@ -1948,7 +1948,7 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
[PCI_IN_19] = {
.test_entry_id = PCI_IN_19_ENTRY,
.module_id = PCIE,
- .rule_desc = "Check Cmd Reg memory space enable",
+ .rule_desc = "Check Command,BIST,and Hdr Cap registers",
.platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI,
.flag = BASE_RULE,
},
@@ -3818,6 +3818,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
[CXL010_ENTRY] = cxl010_entry,
[CXL011_ENTRY] = cxl011_entry,
[CXL013_ENTRY] = cxl013_entry,
+ [M007_ENTRY] = m007_entry,
/* The following test entries are excluded from compilation for the BSA DT UEFI App, as they are
not required for the BSA DT build. These tests invoke VAL APIs, which in turn call PAL APIs,
and PAL_DT lacks a few necessary implementations.*/