diff --git a/memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryRequestPerformanceStatistics.sv b/memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryRequestPerformanceStatistics.sv
index 2895353..474cd8a 100644
--- a/memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryRequestPerformanceStatistics.sv
+++ b/memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryRequestPerformanceStatistics.sv
@@ -1,4 +1,5 @@
 module BankPhysicalMemoryRequestPerformanceStatistics #(
+    parameter int CHANNEL,
     parameter int RANK,
     parameter int BANK,
     parameter int ADDRESS_WIDTH,
@@ -27,7 +28,7 @@ module BankPhysicalMemoryRequestPerformanceStatistics #(
     reg [1023:0] filename;
     
     initial begin
-        $sformat(filename, "bank_req_queue_stats_rank%0d_bank%0d.csv", RANK, BANK);
+        $sformat(filename, "bank_req_queue_stats_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
         file = $fopen(filename, "w");
         $fwrite(file, "RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Type,Cycle\n");
     end
diff --git a/memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryResponsePerformanceStatistics.sv b/memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryResponsePerformanceStatistics.sv
index fbf6d57..f4ba793 100644
--- a/memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryResponsePerformanceStatistics.sv
+++ b/memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryResponsePerformanceStatistics.sv
@@ -1,4 +1,5 @@
 module BankPhysicalMemoryResponsePerformanceStatistics #(
+    parameter int CHANNEL,
     parameter int RANK,
     parameter int BANK,
     parameter int ADDRESS_WIDTH,
@@ -25,7 +26,7 @@ module BankPhysicalMemoryResponsePerformanceStatistics #(
     reg [1023:0] filename;
     
     initial begin
-        $sformat(filename, "bank_resp_queue_stats_rank%0d_bank%0d.csv", RANK, BANK);
+        $sformat(filename, "bank_resp_queue_stats_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
         file = $fopen(filename, "w");
         $fwrite(file, "RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Data,Cycle,ActiveRow,ActiveCol\n");
     end
diff --git a/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPerformanceStatisticsInput.sv b/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPerformanceStatisticsInput.sv
index f12f288..5f71423 100644
--- a/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPerformanceStatisticsInput.sv
+++ b/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPerformanceStatisticsInput.sv
@@ -1,4 +1,5 @@
 module BankSchedulerPerformanceStatisticsInput #(
+    parameter int CHANNEL,
     parameter int RANK,
     parameter int BANK, 
     parameter int ADDRESS_WIDTH,
@@ -19,7 +20,7 @@ module BankSchedulerPerformanceStatisticsInput #(
     reg [1023:0] filename;
 
     initial begin
-        $sformat(filename, "input_request_stats_scheduler_rank%0d_bank%0d.csv", RANK, BANK);
+        $sformat(filename, "input_request_stats_scheduler_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
         file = $fopen(filename, "w");
         $fwrite(file, "RequestID,Address,TypeRd,TypeWr,Cycle\n");
     end
diff --git a/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPerformanceStatisticsOutput.sv b/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPerformanceStatisticsOutput.sv
index a04ba80..6b97cc4 100644
--- a/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPerformanceStatisticsOutput.sv
+++ b/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPerformanceStatisticsOutput.sv
@@ -1,4 +1,5 @@
 module BankSchedulerPerformanceStatisticsOutput #(
+    parameter int CHANNEL,
     parameter int RANK,
     parameter int BANK,
     parameter int ADDRESS_WIDTH,
@@ -37,7 +38,7 @@ module BankSchedulerPerformanceStatisticsOutput #(
     reg [2:0] reqType; // holds 0..7 per table above
 
     initial begin
-        $sformat(filename, "output_response_stats_scheduler_rank%0d_bank%0d.csv", RANK, BANK);
+        $sformat(filename, "output_response_stats_scheduler_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
         file = $fopen(filename, "w");
         // Note header includes TypeID (numeric) to match encoded values above
         $fwrite(file, "RequestID,Address,Data,TypeID,Cycle\n");
diff --git a/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryRequestPerformanceStatistics.sv b/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryRequestPerformanceStatistics.sv
index c674a3d..9c2683c 100644
--- a/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryRequestPerformanceStatistics.sv
+++ b/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryRequestPerformanceStatistics.sv
@@ -1,4 +1,5 @@
 module BankSchedulerPhysicalMemoryRequestPerformanceStatistics #(
+    parameter int CHANNEL,
     parameter int RANK,
     parameter int BANK,
     parameter int ADDRESS_WIDTH,
@@ -45,7 +46,7 @@ module BankSchedulerPhysicalMemoryRequestPerformanceStatistics #(
     reg [2:0] reqType; // holds 0..7 per table above
 
     initial begin
-        $sformat(filename, "memory_request_queue_stats_scheduler_rank%0d_bank%0d.csv", RANK, BANK);
+        $sformat(filename, "memory_request_queue_stats_scheduler_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
         file = $fopen(filename, "w");
         $fwrite(file, "RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Data,TypeID,Cycle\n");
     end
diff --git a/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryResponsePerformanceStatistics.sv b/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryResponsePerformanceStatistics.sv
index d1a498e..c3e21ce 100644
--- a/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryResponsePerformanceStatistics.sv
+++ b/memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryResponsePerformanceStatistics.sv
@@ -1,4 +1,5 @@
 module BankSchedulerPhysicalMemoryResponsePerformanceStatistics #(
+    parameter int CHANNEL,
     parameter int RANK,
     parameter int BANK,
     parameter int ADDRESS_WIDTH,
@@ -23,7 +24,7 @@ module BankSchedulerPhysicalMemoryResponsePerformanceStatistics #(
     reg [1023:0] filename;
 
     initial begin
-        $sformat(filename, "memory_response_queue_stats_scheduler_rank%0d_bank%0d.csv", RANK, BANK);
+        $sformat(filename, "memory_response_queue_stats_scheduler_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
         file = $fopen(filename, "w");
         $fwrite(file, "RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Data,Cycle\n");
     end
diff --git a/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/BankPerformanceStatistics.scala b/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/BankPerformanceStatistics.scala
index 35b77f9..787c4fa 100644
--- a/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/BankPerformanceStatistics.scala
+++ b/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/BankPerformanceStatistics.scala
@@ -12,11 +12,13 @@ import chisel3.util._
   *   - globalCycle: a cycle count for timestamping.
   */
 class BankPhysicalMemoryRequestPerformanceStatistics(
+  val channel:   Int,
   val rank:      Int,
   val bank:      Int,
   val memParams: MemoryConfigurationParameters)
     extends BlackBox(
       Map(
+        "CHANNEL"           -> channel,
         "RANK"              -> rank,
         "BANK"              -> bank,
         "ADDRESS_WIDTH"     -> memParams.addressWidth,
@@ -57,11 +59,13 @@ class BankPhysicalMemoryRequestPerformanceStatistics(
   *   - globalCycle: a cycle count for timestamping.
   */
 class BankPhysicalMemoryResponsePerformanceStatistics(
+  val channel:   Int,
   val rank:      Int,
   val bank:      Int,
   val memParams: MemoryConfigurationParameters)
     extends BlackBox(
       Map(
+        "CHANNEL"           -> channel,
         "RANK"              -> rank,
         "BANK"              -> bank,
         "ADDRESS_WIDTH"     -> memParams.addressWidth,
@@ -116,6 +120,7 @@ class BankPerformanceStatistics(localConfiguration: LocalConfigurationParameters
   // Instantiate the BlackBox modules
   val perfMemRequests  = Module(
     new BankPhysicalMemoryRequestPerformanceStatistics(
+      localConfiguration.channelIndex,
       localConfiguration.rankIndex,
       localConfiguration.bankIndex,
       params
@@ -123,6 +128,7 @@ class BankPerformanceStatistics(localConfiguration: LocalConfigurationParameters
   )
   val perfMemResponses = Module(
     new BankPhysicalMemoryResponsePerformanceStatistics(
+      localConfiguration.channelIndex,
       localConfiguration.rankIndex,
       localConfiguration.bankIndex,
       params
diff --git a/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/SchedulerMemoryPerformanceStatistics.scala b/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/SchedulerMemoryPerformanceStatistics.scala
index 8018957..f64f9ba 100644
--- a/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/SchedulerMemoryPerformanceStatistics.scala
+++ b/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/SchedulerMemoryPerformanceStatistics.scala
@@ -12,11 +12,13 @@ import chisel3.util._
   *   - globalCycle: a cycle count for timestamping.
   */
 class BankSchedulerPhysicalMemoryRequestPerformanceStatistics(
+  val channel:      Int,
   val rank:      Int,
   val bank:      Int,
   val memParams: MemoryConfigurationParameters)
     extends BlackBox(
       Map(
+        "CHANNEL"              -> channel,
         "RANK"              -> rank,
         "BANK"              -> bank,
         "ADDRESS_WIDTH"     -> memParams.addressWidth,
@@ -51,11 +53,13 @@ class BankSchedulerPhysicalMemoryRequestPerformanceStatistics(
 
 /** Monitors responses from physical memory. */
 class BankSchedulerPhysicalMemoryResponsePerformanceStatistics(
+  val channel:      Int,
   val rank:      Int,
   val bank:      Int,
   val memParams: MemoryConfigurationParameters)
     extends BlackBox(
       Map(
+        "CHANNEL"              -> channel,
         "RANK"              -> rank,
         "BANK"              -> bank,
         "ADDRESS_WIDTH"     -> memParams.addressWidth,
diff --git a/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/SchedulerPerformanceStatistics.scala b/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/SchedulerPerformanceStatistics.scala
index e9b7a33..ab00952 100644
--- a/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/SchedulerPerformanceStatistics.scala
+++ b/memorysim/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/SchedulerPerformanceStatistics.scala
@@ -12,11 +12,13 @@ import chisel3.util._
   *   - globalCycle: a cycle count for timestamping.
   */
 class BankSchedulerPerformanceStatisticsInput(
+  val channel:      Int,
   val rank:      Int,
   val bank:      Int,
   val memParams: MemoryConfigurationParameters)
     extends BlackBox(
       Map(
+        "CHANNEL"              -> channel,
         "RANK"              -> rank,
         "BANK"              -> bank,
         "ADDRESS_WIDTH"     -> memParams.addressWidth,
@@ -48,11 +50,13 @@ class BankSchedulerPerformanceStatisticsInput(
   *   - globalCycle: the global cycle counter.
   */
 class BankSchedulerPerformanceStatisticsOutput(
+  val channel:      Int,
   val rank:      Int,
   val bank:      Int,
   val memParams: MemoryConfigurationParameters)
     extends BlackBox(
       Map(
+        "CHANNEL"              -> channel,
         "RANK"              -> rank,
         "BANK"              -> bank,
         "ADDRESS_WIDTH"     -> memParams.addressWidth,
@@ -105,6 +109,7 @@ class BankSchedulerPerformanceStatistics(
   // Instantiate the BlackBox modules
   val perfIn           = Module(
     new BankSchedulerPerformanceStatisticsInput(
+      localConfiguration.channelIndex,
       localConfiguration.rankIndex,
       localConfiguration.bankIndex,
       params
@@ -112,6 +117,7 @@ class BankSchedulerPerformanceStatistics(
   )
   val perfOut          = Module(
     new BankSchedulerPerformanceStatisticsOutput(
+      localConfiguration.channelIndex,
       localConfiguration.rankIndex,
       localConfiguration.bankIndex,
       params
@@ -119,6 +125,7 @@ class BankSchedulerPerformanceStatistics(
   )
   val perfMemRequests  = Module(
     new BankSchedulerPhysicalMemoryRequestPerformanceStatistics(
+      localConfiguration.channelIndex,
       localConfiguration.rankIndex,
       localConfiguration.bankIndex,
       params
@@ -126,6 +133,7 @@ class BankSchedulerPerformanceStatistics(
   )
   val perfMemResponses = Module(
     new BankSchedulerPhysicalMemoryResponsePerformanceStatistics(
+      localConfiguration.channelIndex,
       localConfiguration.rankIndex,
       localConfiguration.bankIndex,
       params