Video Memory Management

[giuliof]

See #3 for diagram of memory interconnections.
From experiments we know that H9 is video memory and contains one character per byte, while J9 is attribute memory and contains graphical attributes for each character.

• How is handled concurrency between Z80 and CRTC during video memory access? (aka, how /CE, /OE, /WE and mux SEL are generated).
• Video memory can be read, but from where? With actual knowledge, data path is only from Z80 to RAM ICs.

[giuliof]

• Concurrency:

  • video ram mux SEL (i.e. the signal that chooses if video ram is addressed by Z80 or CRTC) is the /CRTC "main clock" (1.875MHz). On low level access is reserved to Z80, on high level access is reserved to CRTC.
  • During CRTC phase, character and attribute RAM are accessed together. Then, /CE and /OE are asserted. There is no conflict on Z80 data bus because of the F11/F12 buffers.
  • Z80 phase is a bit more complex because involves a syncronization. Since Z80 clock and CRTC clock are not in phase, a read/write request may fall outside Z80 phase. So, the request is latched (E14 registers) and Z80 is put in WAIT state until actual Z80 phase, where request may be served and WAIT can be deasserted. While Z80 is in WAIT state, CRTC can still access memory during its phase.
  • (hypothesis) write requests (see attached diagram): during WAIT state, Z80 keeps stable addr and data busses, so the data may be sampled by the RAM during WAIT state.
  • (hypothesis) read requests (see attached diagram): as before, but data from the ram is latched first in F12 register. When WAIT is deasserted, Z80 phase is finished and video ram can't be directly accessed anymore, but data is already latched in F12 and can be read from there.

• Read/Write: first schematic was wrong, check new one in Main Memory Management #3.

• Rewrite all this in a friendlier way for ceda-home.