3D2-Lab4/REG_DEFS.s at master · dslogget/3D2-Lab4 · GitHub

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	AREA	REG_DEFS, CODE, READONLY


;IO DEFS
IO0PIN 		EQU		0xE0028000
IO0SET		EQU		0xE0028004
IO0DIR		EQU		0xE0028008
IO0CLR		EQU		0xE002800C
IO1PIN 		EQU		0xE0028010
IO1SET		EQU		0xE0028014
IO1DIR		EQU		0xE0028018
IO1CLR		EQU		0xE002801C


VICVECTADDR 	EQU		0xFFFFF030
VICINTSELECT 	EQU		0xFFFFF00C
VICINTENABLE	EQU		0xFFFFF010
VICDEFVECTADDR	EQU		0xFFFFF034

T0IR		EQU		 0xE0004000
T0TCR		EQU		 0xE0004004
T0TC		EQU		 0xE0004008
T0PR		EQU		 0xE000400C
T0PC		EQU		 0xE0004010
T0MCR		EQU		 0xE0004014
T0MR0		EQU		 0xE0004018
T0MR1		EQU		 0xE000401C
T0MR2		EQU		 0xE0004020
T0MR3		EQU		 0xE0004024
T0CCR		EQU		 0xE0004028
T0CR0		EQU		 0xE000402C
T0CR1		EQU		 0xE0004030
T0CR2		EQU		 0xE0004034
T0CR3		EQU		 0xE0004038
T0EMR		EQU		 0xE000403C
T0CTCR		EQU		 0xE0004070

T1IR		EQU		 0xE0008000
T1TCR		EQU		 0xE0008004
T1TC		EQU		 0xE0008008
T1PR		EQU		 0xE000800C
T1PC		EQU		 0xE0008010
T1MCR		EQU		 0xE0008014
T1MR0		EQU		 0xE0008018
T1MR1		EQU		 0xE000801C
T1MR2		EQU		 0xE0008020
T1MR3		EQU		 0xE0008024
T1CCR		EQU		 0xE0008028
T1CR0		EQU		 0xE000802C
T1CR1		EQU		 0xE0008030
T1CR2		EQU		 0xE0008034
T1CR3		EQU		 0xE0008038
T1EMR		EQU		 0xE000803C
T1CTCR		EQU		 0xE0008070


	END