The Icarus simulation gate has had zero targets since specs/scratch was untracked, and 260 baselines for subjects that do not exist

[gHashTag]

The only ruler in this repository that RUNS generated Verilog is pointed at a directory that does not exist

bootstrap/src/suite.rs:1207:

fn icarus_regression_specs(repo: &Path) -> Vec<PathBuf> {
    collect_t27(&repo.join("specs/scratch"))

specs/scratch was untracked in #2283 and is not in the tree.

$ ls -d specs/scratch                      -> No such file or directory
$ git ls-files specs/scratch | wc -l       -> 0
$ ./target/release/t27c suite --fast --icarus-simulate
--- Phase 3d: Icarus Verilog Simulation Gate ---
Error: phase `icarus-simulate (phase 3d)` has NO targets: <repo>/specs/scratch
       filtered to stems w5*/w3* yielded no .t27 file.
rc=1

The W643 honest floor is doing its job -- the phase refuses rather than reporting
a pass. What nothing says is that the refusal has been the steady state.

• grep -rl icarus .github/workflows/ Makefile -> no hits. Nothing invokes it.
• git ls-files .trinity/icarus-baselines | wc -l -> 260, and 0 of them
  are outside .trinity/icarus-baselines/specs/scratch/. Every tracked baseline
  describes a subject that no longer exists.
• Phase 3e (icarus-cocotb, suite.rs:2263) calls the same selector.

Why it matters more than a dead phase

C, Rust and Zig each have a corpus-walking arm with real targets. The Verilog
arm is the only one that can catch a defect whose whole nature is that it
compiles -- and it is the arm with no targets. Pointed at the corpus by hand:

	specs/
iverilog accepts the SYNTH output (the number this project quotes)	380 of 581
reaches vvp with tests turned on	~170
produces a real PASSED/FAILED verdict	~115
reports failures today	9

The 380 is measured on Verilog with the tests removed.

What the deep ruler found the moment it was pointed somewhere

Four defects, each reproduced with a one-variable control, filed separately:

• real multiplication routed through the integer ladder -- fixed in this pass
• break -> disable fork;, a no-op -- see the sibling issue
• early return inside a loop leaves the loop running -- binary_search does
  not terminate
• every invariant is emitted as a // comment -- Four Verilog-backend findings: 4702 invariants that are comments, and a check that cannot fail #2869

Repair, and the decision in it

Two halves, and only the first is mechanical:

1. Point the selector at a directory that exists.
2. Decide what the baselines mean. 260 files describe subjects that are gone;
   re-baselining against today's corpus records 9 known failures as accepted,
   which is a statement about those 9, not a cleanup.

Not measured here: whether the 9 are compiler defects or spec defects.
They are reported as "a gate that ran would be red today".

Refs #2283

[gHashTag]

The ~ in the table above is now a measurement, and the tool that took it is on master

When I opened this I quoted the funnel with tildes, from a fan-out's numbers.
tri vsim funnel landed as #2993 (eecb818e9) and takes the reading itself.
At 664e21db1:

  specs under specs/                      650

  refused by gen-verilog-for-simulation    69
  iverilog rejected the testbench         410
  simulation exited non-zero                0
  ran and REPORTED FAILURES                 9
  ran and produced a verdict              107
  ran, exit 0, and said NOTHING            55
  timed out at 60s                          0

  650 of 650 accounted for.

So the exact form of the sentence in this issue:

	quoted here	measured
pass the shallow ruler the project reports	380	380
reach vvp with the tests turned on	~170	171 (9 + 107 + 55)
produce a real verdict	~115	116 (9 + 107)
report failures today	9	9

The nine: fpga/bpsk, fpga/mac, fpga/spi, fpga/top_level,
fpga/verification/build_verify, numeric/gft64, numeric/gft128,
numeric/gft256, server/api. It was ten before #2991 merged; trinet/etx
moved to the verdict column and nothing else moved.

One row closed with a clean negative

The 55 that exit 0 having printed nothing: all 55 declare zero test blocks
in source, checked with an independent regex over the .t27 files rather than
by reading the generated Verilog. The testbench is not losing them — there is
nothing there to lose. The row is the honest floor, not a defect.

What is still the decision in this issue

Unchanged. Pointing the selector at a directory that exists is one line. What
those 260 baselines under .trinity/icarus-baselines/specs/scratch/ should
become is not: re-baselining against today's corpus records those nine
failures as accepted, and whether each is a compiler defect or a spec defect
is not established here and is not a walker's question.