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Update test cases for PR #164946 
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+205
-194
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14 files changed

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‎llvm/test/CodeGen/AArch64/tbz-tbnz.ll‎

Lines changed: 5 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -836,30 +836,11 @@ if.then28: ; preds = %if.end26
836836
}
837837

838838
define i1 @avifSequenceHeaderParse() {
839-
; CHECK-SD-LABEL: avifSequenceHeaderParse:
840-
; CHECK-SD: // %bb.0: // %entry
841-
; CHECK-SD-NEXT: mov w8, #1 // =0x1
842-
; CHECK-SD-NEXT: cbz w8, .LBB24_2
843-
; CHECK-SD-NEXT: .LBB24_1: // %bb6
844-
; CHECK-SD-NEXT: mov w0, wzr
845-
; CHECK-SD-NEXT: ret
846-
; CHECK-SD-NEXT: .LBB24_2: // %bb1
847-
; CHECK-SD-NEXT: cbz w8, .LBB24_4
848-
; CHECK-SD-NEXT: // %bb.3:
849-
; CHECK-SD-NEXT: b .LBB24_1
850-
; CHECK-SD-NEXT: .LBB24_4: // %bb2
851-
; CHECK-SD-NEXT: mov w8, #1 // =0x1
852-
; CHECK-SD-NEXT: tbz x8, #63, .LBB24_1
853-
; CHECK-SD-NEXT: // %bb.5: // %bb4
854-
; CHECK-SD-NEXT: mov w8, #1 // =0x1
855-
; CHECK-SD-NEXT: mov w0, wzr
856-
; CHECK-SD-NEXT: ret
857-
;
858-
; CHECK-GI-LABEL: avifSequenceHeaderParse:
859-
; CHECK-GI: // %bb.0: // %entry
860-
; CHECK-GI-NEXT: mov w0, wzr
861-
; CHECK-GI-NEXT: mov w8, #1 // =0x1
862-
; CHECK-GI-NEXT: ret
839+
; CHECK-LABEL: avifSequenceHeaderParse:
840+
; CHECK: // %bb.0: // %entry
841+
; CHECK-NEXT: mov w0, wzr
842+
; CHECK-NEXT: mov w8, #1 // =0x1
843+
; CHECK-NEXT: ret
863844
entry:
864845
%a = icmp slt i64 0, 0
865846
br i1 %a, label %bb1, label %bb6

‎llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll‎

Lines changed: 22 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -14,15 +14,15 @@ define amdgpu_kernel void @uniform_trunc_i16_to_i1(ptr addrspace(1) %out, i16 %x
1414
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
1515
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
1616
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY2]], %subreg.sub0, killed [[COPY1]], %subreg.sub1, killed [[S_MOV_B32_1]], %subreg.sub2, killed [[S_MOV_B32_]], %subreg.sub3
17-
; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[S_LOAD_DWORD_IMM]]
1817
; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 16
19-
; GCN-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[S_LOAD_DWORD_IMM]], killed [[S_MOV_B32_2]], implicit-def dead $scc
18+
; GCN-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_LOAD_DWORD_IMM]], [[S_MOV_B32_2]], implicit-def dead $scc
19+
; GCN-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[S_LOAD_DWORD_IMM]], [[S_MOV_B32_2]], implicit-def dead $scc
2020
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY killed [[S_LSHR_B32_]]
2121
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY3]], implicit-def dead $scc
2222
; GCN-NEXT: S_CMP_EQ_U32 killed [[S_AND_B32_]], 1, implicit-def $scc
2323
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $scc
2424
; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
25-
; GCN-NEXT: S_CMP_LT_I32 killed [[S_SEXT_I32_I16_]], killed [[S_MOV_B32_3]], implicit-def $scc
25+
; GCN-NEXT: S_CMP_LT_I32 killed [[S_LSHL_B32_]], killed [[S_MOV_B32_3]], implicit-def $scc
2626
; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_64 = COPY $scc
2727
; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[COPY5]], killed [[COPY4]], implicit-def dead $scc
2828
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B64_]], implicit $exec
@@ -41,11 +41,12 @@ define i1 @divergent_trunc_i16_to_i1(ptr addrspace(1) %out, i16 %x, i1 %z) {
4141
; GCN-NEXT: {{ $}}
4242
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr3
4343
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
44+
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
45+
; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 killed [[S_MOV_B32_]], [[COPY1]], implicit $exec
4446
; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 1, [[COPY]], implicit $exec
4547
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_AND_B32_e64_]], 1, implicit $exec
46-
; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY1]], 0, 16, implicit $exec
47-
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
48-
; GCN-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I32_e64 killed [[V_BFE_I32_e64_]], killed [[S_MOV_B32_]], implicit $exec
48+
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
49+
; GCN-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I32_e64 killed [[V_LSHLREV_B32_e64_]], killed [[S_MOV_B32_1]], implicit $exec
4950
; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[V_CMP_LT_I32_e64_]], killed [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
5051
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B64_]], implicit $exec
5152
; GCN-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
@@ -124,16 +125,17 @@ define amdgpu_kernel void @uniform_trunc_i64_to_i1(ptr addrspace(1) %out, i64 %x
124125
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
125126
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY4]], %subreg.sub0, killed [[COPY3]], %subreg.sub1, killed [[S_MOV_B32_1]], %subreg.sub2, killed [[S_MOV_B32_]], %subreg.sub3
126127
; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
127-
; GCN-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub2
128-
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY5]], %subreg.sub1
129-
; GCN-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY killed [[S_LOAD_DWORD_IMM]]
130-
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY7]], implicit-def dead $scc
128+
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
129+
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
130+
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[DEF]], %subreg.sub0, killed [[COPY5]], %subreg.sub1
131+
; GCN-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY killed [[S_LOAD_DWORD_IMM]]
132+
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY6]], implicit-def dead $scc
131133
; GCN-NEXT: S_CMP_EQ_U32 killed [[S_AND_B32_]], 1, implicit-def $scc
132-
; GCN-NEXT: [[COPY8:%[0-9]+]]:sreg_64 = COPY $scc
134+
; GCN-NEXT: [[COPY7:%[0-9]+]]:sreg_64 = COPY $scc
133135
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
134-
; GCN-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY killed [[S_MOV_B64_]]
135-
; GCN-NEXT: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I64_e64 killed [[REG_SEQUENCE2]], [[COPY9]], implicit $exec
136-
; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[V_CMP_LT_I64_e64_]], killed [[COPY8]], implicit-def dead $scc
136+
; GCN-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY killed [[S_MOV_B64_]]
137+
; GCN-NEXT: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I64_e64 killed [[REG_SEQUENCE2]], [[COPY8]], implicit $exec
138+
; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[V_CMP_LT_I64_e64_]], killed [[COPY7]], implicit-def dead $scc
137139
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B64_]], implicit $exec
138140
; GCN-NEXT: BUFFER_STORE_BYTE_OFFSET killed [[V_CNDMASK_B32_e64_]], killed [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec :: (store (s8) into %ir.2, addrspace 1)
139141
; GCN-NEXT: S_ENDPGM 0
@@ -146,17 +148,18 @@ define amdgpu_kernel void @uniform_trunc_i64_to_i1(ptr addrspace(1) %out, i64 %x
146148
define i1 @divergent_trunc_i64_to_i1(ptr addrspace(1) %out, i64 %x, i1 %z) {
147149
; GCN-LABEL: name: divergent_trunc_i64_to_i1
148150
; GCN: bb.0 (%ir-block.0):
149-
; GCN-NEXT: liveins: $vgpr2, $vgpr3, $vgpr4
151+
; GCN-NEXT: liveins: $vgpr3, $vgpr4
150152
; GCN-NEXT: {{ $}}
151153
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4
152154
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
153-
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
154-
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1
155+
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
156+
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
157+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[DEF]], %subreg.sub0, [[COPY1]], %subreg.sub1
155158
; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 1, [[COPY]], implicit $exec
156159
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_AND_B32_e64_]], 1, implicit $exec
157160
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
158-
; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[S_MOV_B64_]]
159-
; GCN-NEXT: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I64_e64 killed [[REG_SEQUENCE]], [[COPY3]], implicit $exec
161+
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY killed [[S_MOV_B64_]]
162+
; GCN-NEXT: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I64_e64 killed [[REG_SEQUENCE]], [[COPY2]], implicit $exec
160163
; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[V_CMP_LT_I64_e64_]], killed [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
161164
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B64_]], implicit $exec
162165
; GCN-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]

‎llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll‎

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -391,12 +391,11 @@ define i1 @posnormal_bf16(bfloat %x) nounwind {
391391
; GFX7CHECK: ; %bb.0:
392392
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
393393
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
394-
; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
394+
; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v0
395395
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
396396
; GFX7CHECK-NEXT: v_add_i32_e32 v0, vcc, 0xffffff80, v0
397397
; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0
398398
; GFX7CHECK-NEXT: s_movk_i32 s6, 0x7f00
399-
; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v1
400399
; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
401400
; GFX7CHECK-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
402401
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -467,12 +466,11 @@ define i1 @negnormal_bf16(bfloat %x) nounwind {
467466
; GFX7CHECK: ; %bb.0:
468467
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
469468
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
470-
; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
469+
; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
471470
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
472471
; GFX7CHECK-NEXT: v_add_i32_e32 v0, vcc, 0xffffff80, v0
473472
; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0
474473
; GFX7CHECK-NEXT: s_movk_i32 s6, 0x7f00
475-
; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v1
476474
; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
477475
; GFX7CHECK-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
478476
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -601,11 +599,10 @@ define i1 @negsubnormal_bf16(bfloat %x) nounwind {
601599
; GFX7CHECK: ; %bb.0:
602600
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
603601
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
604-
; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
602+
; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
605603
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
606604
; GFX7CHECK-NEXT: v_add_i32_e64 v0, s[4:5], -1, v0
607605
; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f
608-
; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
609606
; GFX7CHECK-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v0
610607
; GFX7CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
611608
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -826,10 +823,9 @@ define i1 @negfinite_bf16(bfloat %x) nounwind {
826823
; GFX7CHECK: ; %bb.0:
827824
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
828825
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
829-
; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
826+
; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
830827
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
831828
; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
832-
; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
833829
; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v0
834830
; GFX7CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
835831
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -1634,12 +1630,11 @@ define i1 @not_is_plus_normal_bf16(bfloat %x) {
16341630
; GFX7CHECK: ; %bb.0:
16351631
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16361632
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
1637-
; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
1633+
; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
16381634
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
16391635
; GFX7CHECK-NEXT: v_add_i32_e32 v0, vcc, 0xffffff80, v0
16401636
; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0
16411637
; GFX7CHECK-NEXT: s_movk_i32 s6, 0x7eff
1642-
; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v1
16431638
; GFX7CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
16441639
; GFX7CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
16451640
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -1710,12 +1705,11 @@ define i1 @not_is_neg_normal_bf16(bfloat %x) {
17101705
; GFX7CHECK: ; %bb.0:
17111706
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
17121707
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
1713-
; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
1708+
; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v0
17141709
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
17151710
; GFX7CHECK-NEXT: v_add_i32_e32 v0, vcc, 0xffffff80, v0
17161711
; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0
17171712
; GFX7CHECK-NEXT: s_movk_i32 s6, 0x7eff
1718-
; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v1
17191713
; GFX7CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
17201714
; GFX7CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
17211715
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -2068,10 +2062,9 @@ define i1 @not_ispositive_bf16(bfloat %x) {
20682062
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20692063
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
20702064
; GFX7CHECK-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2071-
; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v2, 16, v0
2065+
; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
20722066
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
20732067
; GFX7CHECK-NEXT: s_movk_i32 s6, 0x7f80
2074-
; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2
20752068
; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], s6, v0
20762069
; GFX7CHECK-NEXT: s_mov_b32 s7, 0xff80
20772070
; GFX7CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
@@ -2165,10 +2158,9 @@ define i1 @isnegative_bf16(bfloat %x) {
21652158
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
21662159
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
21672160
; GFX7CHECK-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2168-
; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v2, 16, v0
2161+
; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
21692162
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
21702163
; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
2171-
; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2
21722164
; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v0
21732165
; GFX7CHECK-NEXT: s_mov_b32 s6, 0xff80
21742166
; GFX7CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc

‎llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -570,7 +570,7 @@ define i1 @posnormal_f16(half %x) nounwind {
570570
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
571571
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
572572
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
573-
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
573+
; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
574574
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
575575
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
576576
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -657,7 +657,7 @@ define i1 @negnormal_f16(half %x) nounwind {
657657
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
658658
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
659659
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
660-
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
660+
; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
661661
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
662662
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
663663
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -819,7 +819,7 @@ define i1 @negsubnormal_f16(half %x) nounwind {
819819
; GFX7SELDAG: ; %bb.0:
820820
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
821821
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
822-
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
822+
; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
823823
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
824824
; GFX7SELDAG-NEXT: v_add_i32_e64 v0, s[4:5], -1, v0
825825
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
@@ -1123,7 +1123,7 @@ define i1 @negfinite_f16(half %x) nounwind {
11231123
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11241124
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
11251125
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
1126-
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
1126+
; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
11271127
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
11281128
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
11291129
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v0
@@ -2421,7 +2421,7 @@ define i1 @not_is_plus_normal_f16(half %x) {
24212421
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
24222422
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
24232423
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x77ff
2424-
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
2424+
; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
24252425
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
24262426
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
24272427
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -2517,7 +2517,7 @@ define i1 @not_is_neg_normal_f16(half %x) {
25172517
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
25182518
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
25192519
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x77ff
2520-
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
2520+
; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
25212521
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
25222522
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
25232523
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -3018,7 +3018,7 @@ define i1 @not_ispositive_f16(half %x) {
30183018
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
30193019
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7c00
30203020
; GFX7SELDAG-NEXT: s_mov_b32 s7, 0xfc00
3021-
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
3021+
; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
30223022
; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v0
30233023
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
30243024
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s6, v2
@@ -3109,7 +3109,7 @@ define i1 @isnegative_f16(half %x) {
31093109
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
31103110
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
31113111
; GFX7SELDAG-NEXT: s_mov_b32 s6, 0xfc00
3112-
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
3112+
; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
31133113
; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v0
31143114
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
31153115
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v2

‎llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -702,11 +702,10 @@ entry:
702702
define i32 @vmsk2_sge_allzeros_i8(<32 x i8> %a) {
703703
; LA32-LABEL: vmsk2_sge_allzeros_i8:
704704
; LA32: # %bb.0: # %entry
705-
; LA32-NEXT: vrepli.b $vr2, 0
706-
; LA32-NEXT: vsle.b $vr0, $vr2, $vr0
705+
; LA32-NEXT: vxori.b $vr0, $vr0, 255
707706
; LA32-NEXT: vmskltz.b $vr0, $vr0
708707
; LA32-NEXT: vpickve2gr.hu $a0, $vr0, 0
709-
; LA32-NEXT: vsle.b $vr0, $vr2, $vr1
708+
; LA32-NEXT: vxori.b $vr0, $vr1, 255
710709
; LA32-NEXT: vmskltz.b $vr0, $vr0
711710
; LA32-NEXT: vpickve2gr.hu $a1, $vr0, 0
712711
; LA32-NEXT: slli.w $a1, $a1, 16
@@ -715,11 +714,10 @@ define i32 @vmsk2_sge_allzeros_i8(<32 x i8> %a) {
715714
;
716715
; LA64-LABEL: vmsk2_sge_allzeros_i8:
717716
; LA64: # %bb.0: # %entry
718-
; LA64-NEXT: vrepli.b $vr2, 0
719-
; LA64-NEXT: vsle.b $vr0, $vr2, $vr0
717+
; LA64-NEXT: vxori.b $vr0, $vr0, 255
720718
; LA64-NEXT: vmskltz.b $vr0, $vr0
721719
; LA64-NEXT: vpickve2gr.hu $a0, $vr0, 0
722-
; LA64-NEXT: vsle.b $vr0, $vr2, $vr1
720+
; LA64-NEXT: vxori.b $vr0, $vr1, 255
723721
; LA64-NEXT: vmskltz.b $vr0, $vr0
724722
; LA64-NEXT: vpickve2gr.hu $a1, $vr0, 0
725723
; LA64-NEXT: slli.d $a1, $a1, 16

‎llvm/test/CodeGen/RISCV/bittest.ll‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3553,7 +3553,8 @@ define i32 @bittest_31_slt0_i32(i32 %x, i1 %y) {
35533553
;
35543554
; RV64-LABEL: bittest_31_slt0_i32:
35553555
; RV64: # %bb.0:
3556-
; RV64-NEXT: srliw a0, a0, 31
3556+
; RV64-NEXT: slli a0, a0, 32
3557+
; RV64-NEXT: srli a0, a0, 63
35573558
; RV64-NEXT: and a0, a0, a1
35583559
; RV64-NEXT: ret
35593560
%cmp = icmp slt i32 %x, 0
@@ -3565,14 +3566,14 @@ define i32 @bittest_31_slt0_i32(i32 %x, i1 %y) {
35653566
define i32 @bittest_63_slt0_i64(i32 %x, i1 %y) {
35663567
; RV32-LABEL: bittest_63_slt0_i64:
35673568
; RV32: # %bb.0:
3568-
; RV32-NEXT: srai a0, a0, 31
35693569
; RV32-NEXT: srli a0, a0, 31
35703570
; RV32-NEXT: and a0, a0, a1
35713571
; RV32-NEXT: ret
35723572
;
35733573
; RV64-LABEL: bittest_63_slt0_i64:
35743574
; RV64: # %bb.0:
3575-
; RV64-NEXT: srliw a0, a0, 31
3575+
; RV64-NEXT: slli a0, a0, 32
3576+
; RV64-NEXT: srli a0, a0, 63
35763577
; RV64-NEXT: and a0, a0, a1
35773578
; RV64-NEXT: ret
35783579
%ext = sext i32 %x to i64

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