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4vtomat
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topperc
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[llvm][RISCV] Add bf16 vfabs and vfneg intrinsics for zvfbfa. (#172130)
These are pseudoinstruction aliases for vfsgnjx and vfsgnjn. Co-authored-by: Craig Topper <[email protected]>
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‎clang/include/clang/Basic/riscv_vector.td‎

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@@ -1214,9 +1214,13 @@ defm vfsgnjx : RVVFloatingBinBuiltinSet<HasBF=1>;
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defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "fd">;
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let RequiredFeatures = ["zvfh"] in
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defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "x">;
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let RequiredFeatures = ["zvfbfa"] in
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defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "y">;
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defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "fd">;
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let RequiredFeatures = ["zvfh"] in
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defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "x">;
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let RequiredFeatures = ["zvfbfa"] in
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defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "y">;
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// 13.13. Vector Floating-Point Compare Instructions
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let MaskedPolicyScheme = HasPassthruOperand,

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c‎

Lines changed: 129 additions & 0 deletions
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
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// RUN: -target-feature +experimental-zvfbfa -disable-O0-optnone \
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// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
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// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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#include <riscv_vector.h>
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// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4
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// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[OP1]], <vscale x 1 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
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//
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vbfloat16mf4_t test_vfabs_v_bf16mf4(vbfloat16mf4_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16mf4(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2
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// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[OP1]], <vscale x 2 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
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//
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vbfloat16mf2_t test_vfabs_v_bf16mf2(vbfloat16mf2_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16mf2(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1
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// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[OP1]], <vscale x 4 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
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//
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vbfloat16m1_t test_vfabs_v_bf16m1(vbfloat16m1_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16m1(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2
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// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[OP1]], <vscale x 8 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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vbfloat16m2_t test_vfabs_v_bf16m2(vbfloat16m2_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16m2(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4
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// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[OP1]], <vscale x 16 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
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//
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vbfloat16m4_t test_vfabs_v_bf16m4(vbfloat16m4_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16m4(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8
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// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[OP1]], <vscale x 32 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
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//
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vbfloat16m8_t test_vfabs_v_bf16m8(vbfloat16m8_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16m8(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m
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// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[OP1]], <vscale x 1 x bfloat> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
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//
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vbfloat16mf4_t test_vfabs_v_bf16mf4_m(vbool64_t mask, vbfloat16mf4_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16mf4_m(mask, op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m
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// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[OP1]], <vscale x 2 x bfloat> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
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//
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vbfloat16mf2_t test_vfabs_v_bf16mf2_m(vbool32_t mask, vbfloat16mf2_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16mf2_m(mask, op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m
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// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[OP1]], <vscale x 4 x bfloat> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
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//
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vbfloat16m1_t test_vfabs_v_bf16m1_m(vbool16_t mask, vbfloat16m1_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16m1_m(mask, op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m
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// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[OP1]], <vscale x 8 x bfloat> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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vbfloat16m2_t test_vfabs_v_bf16m2_m(vbool8_t mask, vbfloat16m2_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16m2_m(mask, op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_m
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// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[OP1]], <vscale x 16 x bfloat> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
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//
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vbfloat16m4_t test_vfabs_v_bf16m4_m(vbool4_t mask, vbfloat16m4_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16m4_m(mask, op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_m
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// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[OP1]], <vscale x 32 x bfloat> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
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//
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vbfloat16m8_t test_vfabs_v_bf16m8_m(vbool2_t mask, vbfloat16m8_t op1, size_t vl) {
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return __riscv_vfabs_v_bf16m8_m(mask, op1, vl);
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}
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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c‎

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
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// RUN: -target-feature +experimental-zvfbfa -disable-O0-optnone \
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// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
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// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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#include <riscv_vector.h>
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// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4
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// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[OP1]], <vscale x 1 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
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//
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vbfloat16mf4_t test_vfneg_v_bf16mf4(vbfloat16mf4_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16mf4(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2
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// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[OP1]], <vscale x 2 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
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//
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vbfloat16mf2_t test_vfneg_v_bf16mf2(vbfloat16mf2_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16mf2(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1
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// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[OP1]], <vscale x 4 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
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//
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vbfloat16m1_t test_vfneg_v_bf16m1(vbfloat16m1_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16m1(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2
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// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[OP1]], <vscale x 8 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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vbfloat16m2_t test_vfneg_v_bf16m2(vbfloat16m2_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16m2(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4
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// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[OP1]], <vscale x 16 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
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//
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vbfloat16m4_t test_vfneg_v_bf16m4(vbfloat16m4_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16m4(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8
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// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[OP1]], <vscale x 32 x bfloat> [[OP1]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
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//
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vbfloat16m8_t test_vfneg_v_bf16m8(vbfloat16m8_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16m8(op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m
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// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[OP1]], <vscale x 1 x bfloat> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
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//
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vbfloat16mf4_t test_vfneg_v_bf16mf4_m(vbool64_t mask, vbfloat16mf4_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16mf4_m(mask, op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m
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// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[OP1]], <vscale x 2 x bfloat> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
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//
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vbfloat16mf2_t test_vfneg_v_bf16mf2_m(vbool32_t mask, vbfloat16mf2_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16mf2_m(mask, op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m
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// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[OP1]], <vscale x 4 x bfloat> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
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//
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vbfloat16m1_t test_vfneg_v_bf16m1_m(vbool16_t mask, vbfloat16m1_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16m1_m(mask, op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m
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// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[OP1]], <vscale x 8 x bfloat> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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vbfloat16m2_t test_vfneg_v_bf16m2_m(vbool8_t mask, vbfloat16m2_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16m2_m(mask, op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_m
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// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[OP1]], <vscale x 16 x bfloat> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
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//
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vbfloat16m4_t test_vfneg_v_bf16m4_m(vbool4_t mask, vbfloat16m4_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16m4_m(mask, op1, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_m
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// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x bfloat> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[OP1]], <vscale x 32 x bfloat> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
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//
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vbfloat16m8_t test_vfneg_v_bf16m8_m(vbool2_t mask, vbfloat16m8_t op1, size_t vl) {
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return __riscv_vfneg_v_bf16m8_m(mask, op1, vl);
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}
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