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Merged
AnshKetchum merged 1 commit into from
Oct 2, 2025
Merged

Add channel to verilog #19

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3 changes: 2 additions & 1 deletion memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryRequestPerformanceStatistics.sv
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
module BankPhysicalMemoryRequestPerformanceStatistics #(
parameter int CHANNEL,
parameter int RANK,
parameter int BANK,
parameter int ADDRESS_WIDTH,
Expand Down Expand Up @@ -27,7 +28,7 @@ module BankPhysicalMemoryRequestPerformanceStatistics #(
reg [1023:0] filename;

initial begin
$sformat(filename, "bank_req_queue_stats_rank%0d_bank%0d.csv", RANK, BANK);
$sformat(filename, "bank_req_queue_stats_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
file = $fopen(filename, "w");
$fwrite(file, "RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Type,Cycle\n");
end
Expand Down
3 changes: 2 additions & 1 deletion memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryResponsePerformanceStatistics.sv
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
module BankPhysicalMemoryResponsePerformanceStatistics #(
parameter int CHANNEL,
parameter int RANK,
parameter int BANK,
parameter int ADDRESS_WIDTH,
Expand All @@ -25,7 +26,7 @@ module BankPhysicalMemoryResponsePerformanceStatistics #(
reg [1023:0] filename;

initial begin
$sformat(filename, "bank_resp_queue_stats_rank%0d_bank%0d.csv", RANK, BANK);
$sformat(filename, "bank_resp_queue_stats_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
file = $fopen(filename, "w");
$fwrite(file, "RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Data,Cycle,ActiveRow,ActiveCol\n");
end
Expand Down
3 changes: 2 additions & 1 deletion memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPerformanceStatisticsInput.sv
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
module BankSchedulerPerformanceStatisticsInput #(
parameter int CHANNEL,
parameter int RANK,
parameter int BANK,
parameter int ADDRESS_WIDTH,
Expand All @@ -19,7 +20,7 @@ module BankSchedulerPerformanceStatisticsInput #(
reg [1023:0] filename;

initial begin
$sformat(filename, "input_request_stats_scheduler_rank%0d_bank%0d.csv", RANK, BANK);
$sformat(filename, "input_request_stats_scheduler_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
file = $fopen(filename, "w");
$fwrite(file, "RequestID,Address,TypeRd,TypeWr,Cycle\n");
end
Expand Down
3 changes: 2 additions & 1 deletion memorysim/memctrl/src/main/resources/vsrc/BankSchedulerPerformanceStatisticsOutput.sv
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
module BankSchedulerPerformanceStatisticsOutput #(
parameter int CHANNEL,
parameter int RANK,
parameter int BANK,
parameter int ADDRESS_WIDTH,
Expand Down Expand Up @@ -37,7 +38,7 @@ module BankSchedulerPerformanceStatisticsOutput #(
reg [2:0] reqType; // holds 0..7 per table above

initial begin
$sformat(filename, "output_response_stats_scheduler_rank%0d_bank%0d.csv", RANK, BANK);
$sformat(filename, "output_response_stats_scheduler_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
file = $fopen(filename, "w");
// Note header includes TypeID (numeric) to match encoded values above
$fwrite(file, "RequestID,Address,Data,TypeID,Cycle\n");
Expand Down
3 changes: 2 additions & 1 deletion ...emctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryRequestPerformanceStatistics.sv
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
module BankSchedulerPhysicalMemoryRequestPerformanceStatistics #(
parameter int CHANNEL,
parameter int RANK,
parameter int BANK,
parameter int ADDRESS_WIDTH,
Expand Down Expand Up @@ -45,7 +46,7 @@ module BankSchedulerPhysicalMemoryRequestPerformanceStatistics #(
reg [2:0] reqType; // holds 0..7 per table above

initial begin
$sformat(filename, "memory_request_queue_stats_scheduler_rank%0d_bank%0d.csv", RANK, BANK);
$sformat(filename, "memory_request_queue_stats_scheduler_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
file = $fopen(filename, "w");
$fwrite(file, "RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Data,TypeID,Cycle\n");
end
Expand Down
3 changes: 2 additions & 1 deletion ...mctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryResponsePerformanceStatistics.sv
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
module BankSchedulerPhysicalMemoryResponsePerformanceStatistics #(
parameter int CHANNEL,
parameter int RANK,
parameter int BANK,
parameter int ADDRESS_WIDTH,
Expand All @@ -23,7 +24,7 @@ module BankSchedulerPhysicalMemoryResponsePerformanceStatistics #(
reg [1023:0] filename;

initial begin
$sformat(filename, "memory_response_queue_stats_scheduler_rank%0d_bank%0d.csv", RANK, BANK);
$sformat(filename, "memory_response_queue_stats_scheduler_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
file = $fopen(filename, "w");
$fwrite(file, "RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Data,Cycle\n");
end
Expand Down
6 changes: 6 additions & 0 deletions ...m/memctrl/src/main/scala/memorysim/memctrl/utils/trackers/BankPerformanceStatistics.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,11 +12,13 @@ import chisel3.util._
* - globalCycle: a cycle count for timestamping.
*/
class BankPhysicalMemoryRequestPerformanceStatistics(
val channel: Int,
val rank: Int,
val bank: Int,
val memParams: MemoryConfigurationParameters)
extends BlackBox(
Map(
"CHANNEL" -> channel,
"RANK" -> rank,
"BANK" -> bank,
"ADDRESS_WIDTH" -> memParams.addressWidth,
Expand Down Expand Up @@ -57,11 +59,13 @@ class BankPhysicalMemoryRequestPerformanceStatistics(
* - globalCycle: a cycle count for timestamping.
*/
class BankPhysicalMemoryResponsePerformanceStatistics(
val channel: Int,
val rank: Int,
val bank: Int,
val memParams: MemoryConfigurationParameters)
extends BlackBox(
Map(
"CHANNEL" -> channel,
"RANK" -> rank,
"BANK" -> bank,
"ADDRESS_WIDTH" -> memParams.addressWidth,
Expand Down Expand Up @@ -116,13 +120,15 @@ class BankPerformanceStatistics(localConfiguration: LocalConfigurationParameters
// Instantiate the BlackBox modules
val perfMemRequests = Module(
new BankPhysicalMemoryRequestPerformanceStatistics(
localConfiguration.channelIndex,
localConfiguration.rankIndex,
localConfiguration.bankIndex,
params
)
)
val perfMemResponses = Module(
new BankPhysicalMemoryResponsePerformanceStatistics(
localConfiguration.channelIndex,
localConfiguration.rankIndex,
localConfiguration.bankIndex,
params
Expand Down
4 changes: 4 additions & 0 deletions ...rc/main/scala/memorysim/memctrl/utils/trackers/SchedulerMemoryPerformanceStatistics.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,11 +12,13 @@ import chisel3.util._
* - globalCycle: a cycle count for timestamping.
*/
class BankSchedulerPhysicalMemoryRequestPerformanceStatistics(
val channel: Int,
val rank: Int,
val bank: Int,
val memParams: MemoryConfigurationParameters)
extends BlackBox(
Map(
"CHANNEL" -> channel,
"RANK" -> rank,
"BANK" -> bank,
"ADDRESS_WIDTH" -> memParams.addressWidth,
Expand Down Expand Up @@ -51,11 +53,13 @@ class BankSchedulerPhysicalMemoryRequestPerformanceStatistics(

/** Monitors responses from physical memory. */
class BankSchedulerPhysicalMemoryResponsePerformanceStatistics(
val channel: Int,
val rank: Int,
val bank: Int,
val memParams: MemoryConfigurationParameters)
extends BlackBox(
Map(
"CHANNEL" -> channel,
"RANK" -> rank,
"BANK" -> bank,
"ADDRESS_WIDTH" -> memParams.addressWidth,
Expand Down
8 changes: 8 additions & 0 deletions ...ctrl/src/main/scala/memorysim/memctrl/utils/trackers/SchedulerPerformanceStatistics.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,11 +12,13 @@ import chisel3.util._
* - globalCycle: a cycle count for timestamping.
*/
class BankSchedulerPerformanceStatisticsInput(
val channel: Int,
val rank: Int,
val bank: Int,
val memParams: MemoryConfigurationParameters)
extends BlackBox(
Map(
"CHANNEL" -> channel,
"RANK" -> rank,
"BANK" -> bank,
"ADDRESS_WIDTH" -> memParams.addressWidth,
Expand Down Expand Up @@ -48,11 +50,13 @@ class BankSchedulerPerformanceStatisticsInput(
* - globalCycle: the global cycle counter.
*/
class BankSchedulerPerformanceStatisticsOutput(
val channel: Int,
val rank: Int,
val bank: Int,
val memParams: MemoryConfigurationParameters)
extends BlackBox(
Map(
"CHANNEL" -> channel,
"RANK" -> rank,
"BANK" -> bank,
"ADDRESS_WIDTH" -> memParams.addressWidth,
Expand Down Expand Up @@ -105,27 +109,31 @@ class BankSchedulerPerformanceStatistics(
// Instantiate the BlackBox modules
val perfIn = Module(
new BankSchedulerPerformanceStatisticsInput(
localConfiguration.channelIndex,
localConfiguration.rankIndex,
localConfiguration.bankIndex,
params
)
)
val perfOut = Module(
new BankSchedulerPerformanceStatisticsOutput(
localConfiguration.channelIndex,
localConfiguration.rankIndex,
localConfiguration.bankIndex,
params
)
)
val perfMemRequests = Module(
new BankSchedulerPhysicalMemoryRequestPerformanceStatistics(
localConfiguration.channelIndex,
localConfiguration.rankIndex,
localConfiguration.bankIndex,
params
)
)
val perfMemResponses = Module(
new BankSchedulerPhysicalMemoryResponsePerformanceStatistics(
localConfiguration.channelIndex,
localConfiguration.rankIndex,
localConfiguration.bankIndex,
params
Expand Down
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