fix(rni): two-packet write txdat send trigger lost

[liuwuyu118]

Problem

In rni_awctrl, for two-packet write entries (e.g. 64B write = 2x32B CHI data flits), the second packet's send trigger (txdat_rdy_entry_d3_q & txdat_select_vec_d3_q) may assert while awctrl_txdat_not_busy_d2_i is still low, because the write buffer is still assembling the first flit. By the time not_busy_d2 reasserts, rdy_d3 has already been cleared. This causes txdat_send_vec to never be set for the second packet, and the write transaction hangs.

Root Cause

The original combinational assign gates the send trigger with not_busy_d2, but rdy_d3 is only high for one cycle. When these two signals do not overlap, the trigger is lost.

Before:

assign txdat_send_vec_ns_w = (txdat_send_vec_q
    | ({N{awctrl_txdat_not_busy_d2_i}} & txdat_rdy_entry_d3_q & txdat_select_vec_d3_q))
    & ~awctrl_entry_dealloc_vec_w;

Fix

Add a txdat_send_pending_q register that latches (rdy_d3 & sel_d3) and holds it until not_busy_d2 allows propagation into txdat_send_vec. The pending bit is cleared once txdat_send_vec is set or the entry is deallocated.

After:

wire txdat_send_trigger_w = txdat_rdy_entry_d3_q & txdat_select_vec_d3_q;

// latch trigger until not_busy_d2 allows propagation
reg  txdat_send_pending_q;
always @(posedge clk_i or posedge rst_i)
    txdat_send_pending_q <= rst_i ? 0
        : (txdat_send_pending_q | txdat_send_trigger_w)
          & ~txdat_send_vec_q & ~awctrl_entry_dealloc_vec_w;

assign txdat_send_vec_ns_w = (txdat_send_vec_q
    | ({N{awctrl_txdat_not_busy_d2_i}} & (txdat_send_trigger_w | txdat_send_pending_q)))
    & ~awctrl_entry_dealloc_vec_w;

Affected file: rtl/src/rni/rni_awctrl.v

[liuwuyu118]

Closing this in favour of the root-cause fix.

This PR patches a real defect but only its lost-flag symptom. The actual mechanism is that rni_awctrl's two d3 shadow registers (txdat_rdy_entry_d3_q, txdat_select_vec_d3_q) shift unconditionally while the rni_wr_buffer d3 flit register they shadow is stall-enabled — so the misalignment is not specific to two-packet writes, and my txdat_send_pending_q side-latch leaves the wrong-entry and early-set modes open (the latter reuses a TxnID against an outstanding write, violating SS2.5.2).

The correct fix is to gate both shadow registers with the same awctrl_txdat_not_busy_d2_i enable the shadowed stage already uses — one enable each, all three modes closed at the source. That has been adjudicated, reproduced, and merged downstream: 10x-Engineers#104 (supersedes 10x-Engineers#30, the port of this PR).

Recommend maintainers take the shadow-enable approach rather than this side-latch. Thanks to @umerimran-10xe for running it down.