pwm: spacemit: Add Support for K3 SoC - #319
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mainline inclusion from mainline-6.12-rc6 commit 5bb5ccb category: feature bugzilla: RVCK-Project#256 -------------------------------- Introduce basic guest support in perf, enabling it to distinguish between PMU interrupts in the host or guest, and collect fundamental information. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/a67d527dc1b11493fe11f7f53584772fdd983744.1728957131.git.zhouquan@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit eded675 category: feature bugzilla: RVCK-Project#256 -------------------------------- For the information collected on the host side, we need to identify which data originates from the guest and record these events separately, this can be achieved by having KVM register perf callbacks. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/00342d535311eb0629b9ba4f1e457a48e2abee33.1728957131.git.zhouquan@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit e403a90 category: feature bugzilla: RVCK-Project#256 -------------------------------- Order the object files alphabetically in the Makefile so that it is very predictable inserting new object files in the future. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit b6114a7 category: feature bugzilla: RVCK-Project#256 -------------------------------- We will be optimizing HSTATUS CSR access via shared memory setup using the SBI nested acceleration extension. To facilitate this, we first move HSTATUS save/restore in kvm_riscv_vcpu_enter_exit(). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit b922307 category: feature bugzilla: RVCK-Project#256 -------------------------------- The SCOUNTEREN CSR need not be saved/restored in the low-level __kvm_riscv_switch_to() function hence move the SCOUNTEREN CSR save/restore to the kvm_riscv_vcpu_swap_in_guest_state() and kvm_riscv_vcpu_swap_in_host_state() functions in C sources. Also, re-arrange the CSR save/restore and related GPR usage in the low-level __kvm_riscv_switch_to() low-level function. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit 8f57ada category: feature bugzilla: RVCK-Project#256 -------------------------------- Break down the __kvm_riscv_switch_to() function into macros so that these macros can be later re-used by SBI NACL extension based low-level switch function. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-5-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit 5d8f7ee category: feature bugzilla: RVCK-Project#256 -------------------------------- The aia_set_hvictl() internally writes the HVICTL CSR which makes it difficult to optimize the CSR write using SBI NACL extension for kvm_riscv_vcpu_aia_update_hvip() function so replace aia_set_hvictl() with new aia_hvictl_value() which only computes the HVICTL value. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-6-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit 15ff2ff category: feature bugzilla: RVCK-Project#256 -------------------------------- No need to setup SGEI local interrupt when there are zero guest external interrupts (i.e. zero HW IMSIC guest files). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-7-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit 5daf89e category: feature bugzilla: RVCK-Project#256 -------------------------------- Add defines for the new SBI nested acceleration extension which was ratified as part of the SBI v2.0 specification. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-8-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit d466c19 category: feature bugzilla: RVCK-Project#256 -------------------------------- Add a common nested acceleration support which will be shared by all parts of KVM RISC-V. This nested acceleration support detects and enables SBI NACL extension usage based on static keys which ensures minimum impact on the non-nested scenario. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-9-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit e28e6b6 category: feature bugzilla: RVCK-Project#256 -------------------------------- When running under some other hypervisor, prefer nacl_csr_xyz() for accessing H-extension CSRs in the run-loop. This makes CSR access faster whenever SBI nested acceleration is available. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-10-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit dab5560 category: feature bugzilla: RVCK-Project#256 -------------------------------- When running under some other hypervisor, prefer nacl_csr_xyz() for accessing AIA CSRs in the run-loop. This makes CSR access faster whenever SBI nested acceleration is available. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-11-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit 68c72a6 category: feature bugzilla: RVCK-Project#256 -------------------------------- Implement an optimized KVM world-switch using SBI sync SRET call when SBI nested acceleration extension is available. This improves KVM world-switch when KVM RISC-V is running as a Guest under some other hypervisor. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-12-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit 3e7d154 category: feature bugzilla: RVCK-Project#256 -------------------------------- Save trap CSRs in the kvm_riscv_vcpu_enter_exit() function instead of the kvm_arch_vcpu_ioctl_run() function so that HTVAL and HTINST CSRs are accessed in more optimized manner while running under some other hypervisor. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-13-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit 5bdecd8 category: feature bugzilla: RVCK-Project#256 -------------------------------- When running under some other hypervisor, use SBI NACL based HFENCEs for TLB shoot-down via KVM requests. This makes HFENCEs faster whenever SBI nested acceleration is available. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-14-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.10-rc1 commit 197bd23 category: feature bugzilla: RVCK-Project#263 -------------------------------- 'vlenb', added to riscv_v_ext_state by commit c35f3aa ("RISC-V: vector: export VLENB csr in __sc_riscv_v_state"), isn't being initialized in guest_context. If we export 'vlenb' as a KVM CSR, something we want to do in the next patch, it'll always return 0. Set 'vlenb' to riscv_v_size/32. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.10-rc1 commit 2fa2903 category: feature bugzilla: RVCK-Project#263 -------------------------------- Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise it is not possible to retrieve any vector reg since we're returning EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-v6.17-rc4 commit 7997662 category: feature bugzilla: RVCK-Project#263 -------------------------------- The userspace load can put up to 2048 bits into an xlen bit stack buffer. We want only xlen bits, so check the size beforehand. Fixes: 2fa2903 ("RISC-V: KVM: add 'vlenb' Vector CSR") Cc: stable@vger.kernel.org Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Link: https://lore.kernel.org/r/20250805104418.196023-4-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17-rc5 commit a03ee11 category: feature bugzilla: RVCK-Project#265 -------------------------------- We did not propagate the __user attribute of the pointers in __get_kernel_nofault() and __put_kernel_nofault(), which results in sparse complaining: >> mm/maccess.c:41:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void const [noderef] __user *from @@ got unsigned long long [usertype] * @@ mm/maccess.c:41:17: sparse: expected void const [noderef] __user *from mm/maccess.c:41:17: sparse: got unsigned long long [usertype] * So fix this by correctly casting those pointers. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202508161713.RWu30Lv1-lkp@intel.com/ Suggested-by: Al Viro <viro@zeniv.linux.org.uk> Fixes: f6bff78 ("riscv: uaccess: use 'asm_goto_output' for get_user()") Cc: stable@vger.kernel.org Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Cyril Bur <cyrilbur@tenstorrent.com> Link: https://lore.kernel.org/r/20250903-dev-alex-sparse_warnings_v1-v1-2-7e6350beb700@rivosinc.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.16-rc7 commit b65ca21 category: feature bugzilla: RVCK-Project#265 -------------------------------- After a recent change in clang to strengthen uninitialized warnings [1], there is a warning from val being uninitialized in __put_user_nocheck when called from futex_put_value(): kernel/futex/futex.h:326:18: warning: variable 'val' is uninitialized when used within its own initialization [-Wuninitialized] 326 | unsafe_put_user(val, to, Efault); | ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~ arch/riscv/include/asm/uaccess.h:464:21: note: expanded from macro 'unsafe_put_user' 464 | __put_user_nocheck(x, (ptr), label) | ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~ arch/riscv/include/asm/uaccess.h:314:36: note: expanded from macro '__put_user_nocheck' 314 | __inttype(x) val = (__inttype(x))x; \ | ~~~ ^ While not on by default, -Wshadow flags the same mistake: kernel/futex/futex.h:326:2: warning: declaration shadows a local variable [-Wshadow] 326 | unsafe_put_user(val, to, Efault); | ^ arch/riscv/include/asm/uaccess.h:464:2: note: expanded from macro 'unsafe_put_user' 464 | __put_user_nocheck(x, (ptr), label) | ^ arch/riscv/include/asm/uaccess.h:314:16: note: expanded from macro '__put_user_nocheck' 314 | __inttype(x) val = (__inttype(x))x; \ | ^ kernel/futex/futex.h:320:48: note: previous declaration is here 320 | static __always_inline int futex_put_value(u32 val, u32 __user *to) | ^ Use a three underscore prefix for the val variable in __put_user_nocheck to avoid clashing with either val or __val, which are both used within the put_user macros, clearing up all warnings. Closes: ClangBuiltLinux/linux#2109 Fixes: ca1a66c ("riscv: uaccess: do not do misaligned accesses in get/put_user()") Link: llvm/llvm-project@2464313 [1] Signed-off-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20250715-riscv-uaccess-fix-self-init-val-v1-1-82b8e911f120@kernel.org Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17-rc5 commit 1046791 category: feature bugzilla: RVCK-Project#265 -------------------------------- The type of the value to write should be determined by the size of the destination, not by the value itself, which may be a constant. This aligns the behavior with x86_64, where __typeof__(*(__gu_ptr)) is used to infer the correct type. This fixes an issue in put_cmsg, which was only writing 4 out of 8 bytes to the cmsg_len field, causing the glibc tst-socket-timestamp test to fail. Fixes: ca1a66c ("riscv: uaccess: do not do misaligned accesses in get/put_user()") Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250724220853.1969954-1-aurelien@aurel32.net Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.16-rc2 commit 2aa5801 category: feature bugzilla: RVCK-Project#265 -------------------------------- I must have lost this rebasing things during the merge window, I know I got it at some point but it's not here now. Without this I get warnings along the lines of include/linux/fs.h:3975:15: warning: label followed by a declaration is a C23 extension [-Wc23-extensions] 3975 | if (unlikely(get_user(c, path))) | ^ arch/riscv/include/asm/uaccess.h:274:3: note: expanded from macro 'get_user' 274 | __get_user((x), __p) : \ | ^ arch/riscv/include/asm/uaccess.h:244:2: note: expanded from macro '__get_user' 244 | __get_user_error(__gu_val, __gu_ptr, __gu_err); \ | ^ arch/riscv/include/asm/uaccess.h:207:2: note: expanded from macro '__get_user_error' 207 | __ge LD [M] net/802/psnap.ko t_user_nocheck(x, ptr, __gu_failed); \ | ^ arch/riscv/include/asm/uaccess.h:196:3: note: expanded from macro '__get_user_nocheck' 196 | __get_user_8((x), __gu_ptr, label); \ | ^ arch/riscv/include/asm/uaccess.h:130:2: note: expanded from macro '__get_user_8' 130 | u32 __user *__ptr = (u32 __user *)(ptr); \ | ^ Link: https://lore.kernel.org/r/20250610213058.24852-1-palmer@dabbelt.com Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Cc: stable@vger.kernel.org Fixes: f6bff78 ("riscv: uaccess: use 'asm_goto_output' for get_user()") Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17-rc5 commit fef7ded category: feature bugzilla: RVCK-Project#265 -------------------------------- We used to assign 0 to x without an appropriate cast which results in sparse complaining when x is a pointer: >> block/ioctl.c:72:39: sparse: sparse: Using plain integer as NULL pointer So fix this by casting 0 to the correct type of x. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202508062321.gHv4kvuY-lkp@intel.com/ Fixes: f6bff78 ("riscv: uaccess: use 'asm_goto_output' for get_user()") Cc: stable@vger.kernel.org Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Cyril Bur <cyrilbur@tenstorrent.com> Link: https://lore.kernel.org/r/20250903-dev-alex-sparse_warnings_v1-v1-1-7e6350beb700@rivosinc.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17-rc5 commit 265d6ab category: feature bugzilla: RVCK-Project#265 -------------------------------- During switch to csrs will OR the value of the register into the corresponding csr. In this case we're only interested in restoring the SUM bit not the entire register. Signed-off-by: Cyril Bur <cyrilbur@tenstorrent.com> Link: https://lore.kernel.org/r/20250522160954.429333-1-cyrilbur@tenstorrent.com Co-developed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Fixes: 788aa64 ("riscv: save the SR_SUM status over switches") Link: https://lore.kernel.org/r/20250602121543.1544278-1-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17-rc1 commit 4a50578 category: feature bugzilla: RVCK-Project#257 -------------------------------- The kvm_riscv_vcpu_alloc_vector_context() does return an error code upon failure so don't ignore this in kvm_arch_vcpu_create(). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/20250618113532.471448-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17-rc1 commit 7c67de2 category: feature bugzilla: RVCK-Project#257 -------------------------------- The kvm_riscv_vcpu_aia_init() does not return any failure so drop the return value which is always zero. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/20250618113532.471448-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17-rc1 commit b79bf20 category: feature bugzilla: RVCK-Project#257 -------------------------------- The kvm_riscv_local_tlb_sanitize() deals with sanitizing current VMID related TLB mappings when a VCPU is moved from one host CPU to another. Let's move kvm_riscv_local_tlb_sanitize() to VMID management sources and rename it to kvm_riscv_gstage_vmid_sanitize(). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/20250618113532.471448-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17-rc1 commit 7584eb6 category: feature bugzilla: RVCK-Project#257 -------------------------------- The KVM_REQ_HFENCE_GVMA_VMID_ALL is same as KVM_REQ_TLB_FLUSH so to avoid confusion let's replace KVM_REQ_HFENCE_GVMA_VMID_ALL with KVM_REQ_TLB_FLUSH. Also, rename kvm_riscv_hfence_gvma_vmid_all_process() to kvm_riscv_tlb_flush_process(). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/20250618113532.471448-5-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17-rc1 commit eaa98ba category: feature bugzilla: RVCK-Project#257 -------------------------------- The gstage_set_pte() and gstage_op_pte() should flush TLB only when a leaf PTE changes so that unnecessary TLB flushes can be avoided. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/20250618113532.471448-6-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17-rc1 commit ca539ba category: feature bugzilla: RVCK-Project#257 -------------------------------- The kvm_arch_flush_remote_tlbs_range() expected by KVM core can be easily implemented for RISC-V using kvm_riscv_hfence_gvma_vmid_gpa() hence provide it. Also with kvm_arch_flush_remote_tlbs_range() available for RISC-V, the mmu_wp_memory_region() can happily use kvm_flush_remote_tlbs_memslot() instead of kvm_flush_remote_tlbs(). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/20250618113532.471448-7-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-7.2-rc1 commit 49400b7 category: feature bugzilla: RVCK-Project#320 -------------------------------- The driver's existing logic for setting the DMA mask for "marvell,pdma-1.0" was flawed. It incorrectly relied on pdev->dev->coherent_dma_mask instead of declaring the hardware's fixed addressing capability. A cleaner and more correct approach is to define the mask directly based on the hardware limitations. The MMP/PXA PDMA controller is a 32-bit DMA engine. This is supported by datasheets and various dtsi files for PXA25x, PXA27x, PXA3xx, and MMP2, all of which are 32-bit systems. This patch simplifies the driver's logic by replacing the 'u64 dma_mask' field with a simpler 'u32 dma_width' to store the addressing capability in bits. The complex if/else block in probe() is then replaced with a single, clear call to dma_set_mask_and_coherent(). This sets a fixed 32-bit DMA mask for "marvell,pdma-1.0" and a 64-bit mask for "spacemit,k1-pdma," matching each device's hardware capabilities. Finally, this change also works around a specific build error encountered with clang-20 on x86_64 allyesconfig. The shift-count-overflow error is caused by a known clang compiler issue where the DMA_BIT_MASK(n) macro's ternary operator is not correctly evaluated in static initializers. By moving the macro's evaluation into the probe() function, the driver avoids this compiler bug. Fixes: 5cfe585 ("dmaengine: mmp_pdma: Add SpacemiT K1 PDMA support with 64-bit addressing") Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org> Closes: https://lore.kernel.org/lkml/CA+G9fYsPcMfW-e_0_TRqu4cnwqOqYF3aJOeKUYk6Z4qRStdFvg@mail.gmail.com Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Guodong Xu <guodong@riscstar.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Nathan Chancellor <nathan@kernel.org> # build Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit f46b476 category: feature bugzilla: RVCK-Project#320 -------------------------------- Refactor the DRCMR macro into a helper function mmp_pdma_get_drcmr() to support variable extended DRCMR base addresses across different PDMA implementations, such as SpacemiT K3. Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://patch.msgid.link/20260518-k3-pdma-v6-2-67fdf319a8f8@linux.spacemit.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit 6587b86 category: feature bugzilla: RVCK-Project#320 -------------------------------- SpacemiT K3 reuses most of the PDMA IP design found on K1, with one difference being the extended DRCMR base address. Add "spacemit,k3-pdma" compatible string and define a new mmp_pdma_ops for K3 PDMA. Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://patch.msgid.link/20260518-k3-pdma-v6-3-67fdf319a8f8@linux.spacemit.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit 3f47ca8 category: feature bugzilla: RVCK-Project#320 Added `interrupt-parent = <&saplic>;` to the PDMA node in k3.dtsi, because the `soc` node in our v6.6 tree does not inherit the interrupt controller context globally. -------------------------------- Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. The PDMA controller provides general-purpose DMA capabilities for various peripheral devices across the system to offload CPU data transfers. Unlike the previous K1 SoC, where some DMA masters had memory addressing limitations (e.g. restricted to the 0-4GB space) requiring a dedicated dma-bus with dma-ranges to restrict memory allocations, the K3 DMA masters have full memory addressing capabilities. Therefore, the PDMA node is now instantiated directly under the main soc bus. Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://patch.msgid.link/20260518-k3-pdma-v6-4-67fdf319a8f8@linux.spacemit.com Signed-off-by: Yixun Lan <dlan@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
category: feature bugzilla: RVCK-Project#320 -------------------------------- Enable DMA support Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
dmaengine: Add Peripheral DMA support for SpacemiT K3 SoC
riscv: defconfig: Enable CONFIG_RTC_DRV_EFI config
Fix module load issue for R_RISCV_32_PCREL
…onfig dist inclusion category: cleanup Link: RVCK-Project#251 -------------------------------- The RVCK kernel currently reuses the generic defconfig from linux-6.6.y. Sharing this defconfig introduces potential risks, such as missing relevant fix patches. This patch simply duplicates the existing defconfig and renames the copy to rvck_defconfig. No functional changes are introduced. Signed-off-by: Yanteng Si <siyanteng@iscas.ac.cn>
dist inclusion category: cleanup Link: RVCK-Project#251 -------------------------------- RVCK is a unified RISC-V kernel project that integrates vendor-specific downstream kernels from multiple manufacturers. It resolves cross-vendor conflicts and maintains a single codebase capable of booting all supported boards. Introducing too many BSP-exclusive configs will gradually fragment the unified codebase. This patch cleans up these redundant configurations. Signed-off-by: Yanteng Si <siyanteng@iscas.ac.cn>
dist inclusion category: cleanup Link: RVCK-Project#251 -------------------------------- Restore all config files aligned with upstream linux-6.6.y. The latest stable upstream tag at present is linux-6.6.143. Signed-off-by: Yanteng Si <siyanteng@iscas.ac.cn>
config: 基于 linux-6.6.143 清理并标准化内核默认配置
mainline inclusion from mainline-v6.9-rc1 commit bdc585f ("dt-bindings: pxa-pwm: Convert to YAML") category: feature bugzilla: RVCK-Project#317 -------------------------------- Convert the PXA PWM binding file from TXT to YAML. The original binding does not mention any clocks, but the PWM controller will not probe without a clock. Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240107-pxa-pwm-yaml-v3-1-92ac90911c3f@skole.hr Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-v6.10-rc1 commit b3d8d12 ("dt-bindings: pwm: marvell,pxa: Do not require pwm-cells twice") category: feature bugzilla: RVCK-Project#317 -------------------------------- pwm-cells property is already required by pwm.yaml schema. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/06765e0dd9a842dc51ff9c9cea93f26b8792e44b.1714450308.git.zhoubinbin@loongson.cn Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-v6.17-rc1 commit 08e0b98 ("dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K1 PWM support") category: feature bugzilla: RVCK-Project#317 -------------------------------- The SpacemiT K1 SoC reuses the Marvell PXA910-compatible PWM controller with one notable difference: the addition of a resets property. To make the device tree pass schema validation (make dtbs_check W=3), this patch updates the binding to accept spacemit,k1-pwm as a compatible string, when used in conjunction with the fallback marvell,pxa910-pwm. Support for the optional resets property is also added, as it is required by the K1 integration but was not present in the original Marvell bindings. Since the PWM reset line may be deasserted during the early bootloader stage, making the resets property optional avoids potential double-deassertion, which could otherwise cause flickering on displays that use PWM for backlight control. Additionally, this patch adjusts the required value of the #pwm-cells property for the new compatible string: - For "spacemit,k1-pwm", #pwm-cells must be set to 3. - For existing Marvell compatibles, #pwm-cells remains 1. Background of #pwm-cells change is by an ongoing community discussion about increasing the #pwm-cells value from 1 to 3 for all Marvell PXA PWM devices. These devices are currently the only ones whose bindings do not pass the line index as the first argument. See [1] for further details. [1] https://lore.kernel.org/all/cover.1738842938.git.u.kleine-koenig@baylibre.com/ Reviewed-by: Rob Herring (Arm) <robh@kernel.org> # v2 Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20250429085048.1310409-2-guodong@riscstar.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-v7.2-rc1 commit e7abbff category: feature bugzilla: RVCK-Project#317 -------------------------------- The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 generation, while the difference is that one additional bus clock is added. Signed-off-by: Yixun Lan <dlan@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260428-03-k3-pwm-drv-v2-1-a532bbe45556@kernel.org Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit 384461a category: feature bugzilla: RVCK-Project#317 -------------------------------- Instead of requiring each driver to care for assigning the owner member of struct pwm_ops, handle that implicitly using a macro. Note that the owner member has to be moved to struct pwm_chip, as the ops structure usually lives in read-only memory and so cannot be modified. The upside is that new low level drivers cannot forget the assignment and save one line each. The pwm-crc driver didn't assign .owner, that's not a problem in practice though as the driver cannot be compiled as a module. Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> # Intel LPSS Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> # pwm-{bcm,brcm}*.c Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> # sun4i Acked-by: Andi Shyti <andi.shyti@kernel.org> Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> # pwm-visconti Acked-by: Heiko Stuebner <heiko@sntech.de> # pwm-rockchip Acked-by: Michael Walle <michael@walle.cc> # pwm-sl28cpld Acked-by: Neil Armstrong <neil.armstrong@linaro.org> # pwm-meson Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230804142707.412137-2-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
category: feature bugzilla: RVCK-Project#317 -------------------------------- Remove .owner in pwm_ops which is automatically assigned during chip registration. Dependency patch "pwm: Manage owner assignment implicitly for drivers". Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit 87e51b7 category: feature bugzilla: RVCK-Project#317 -------------------------------- The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit 4e77431 category: feature bugzilla: RVCK-Project#317 -------------------------------- Apart from the two of_xlate implementations this member is write-only. In the of_xlate functions of_pwm_xlate_with_flags() and of_pwm_single_xlate() it's more sensible to check for args->args_count because this is what is actually used in the device tree. Acked-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/53d8c545aa8f79a920358be9e72e382b3981bdc4.1704835845.git.u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit 8aebd72 category: feature bugzilla: RVCK-Project#317 RVCK's PWM core lacks devm_pwmchip_alloc() (and pwmchip_get_drvdata()), so upstream conversion cannot be applied directly; keep the embedded struct pwm_chip model. -------------------------------- This prepares the pwm-pxa driver to further changes of the pwm core outlined in the commit introducing devm_pwmchip_alloc(). There is no intended semantical change and the driver should behave as before. Link: https://lore.kernel.org/r/bee8ae436a9dfb8539637cbb7269a208f787a62a.1707900770.git.u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit 2c69747 category: feature bugzilla: RVCK-Project#317 -------------------------------- make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pwm/pwm-imx1.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pwm/pwm-imx27.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pwm/pwm-intel-lgm.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pwm/pwm-mediatek.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pwm/pwm-pxa.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pwm/pwm-samsung.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pwm/pwm-spear.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pwm/pwm-visconti.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Link: https://lore.kernel.org/r/20240610-md-drivers-pwm-v2-1-b337cfaa70ea@quicinc.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit df08fff category: feature bugzilla: RVCK-Project#317 -------------------------------- Add a message to the error path of devm_clk_get() and simplify the error path of devm_pwmchip_add() while improving the error message en passant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20250313072855.3360076-2-u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit 52d2d14 category: feature bugzilla: RVCK-Project#317 The helper function devm_reset_control_get_optional_exclusive_deasserted() was introduced in newer kernel versions and is not available in Linux 6.6. To maintain compatibility with Linux 6.6, the driver must explicitly acquire the reset controller via devm_reset_control_get_optional() and handle the deassertion pulse manually. -------------------------------- Support optional reset control for the PWM PXA driver. During probe, it acquires the reset controller using devm_reset_control_get_optional_exclusive_deasserted() to get and deassert the reset controller to enable the PWM channel. Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20250429085048.1310409-3-guodong@riscstar.com [ukleinek: Fix conflict with commit df08fff ("pwm: pxa: Improve using dev_err_probe()")] Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit 74bca0f category: feature bugzilla: RVCK-Project#317 -------------------------------- Add one secondary optional bus clock for the PWM PXA driver, also keep it compatible with old single clock. The SpacemiT K3 SoC require a bus clock for PWM controller, acquire and enable it during probe phase. Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260428-03-k3-pwm-drv-v2-2-a532bbe45556@kernel.org Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit 844c291 category: feature bugzilla: RVCK-Project#317 -------------------------------- Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents the pinctrl info which would easily help to enable them in future. Link: https://patch.msgid.link/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org Signed-off-by: Yixun Lan <dlan@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/30891790003 参数解析结果
测试完成 详细结果:
Kunit Test Result[08:27:56] Testing complete. Ran 482 tests: passed: 465, skipped: 17
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rvck-6.6已经rebase，请rebase后push -f开发分支。 |
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fixed: #317
Description
Introduces PWM controller support for the SpacemiT K3 SoC.
The implementation is based on the upstream patches for the
pxa_pwmdriver. Due to significant context differences and API changes between upstream (v7.x) and our current tree (v6.6).Therefore, this PR separates the upstream logic into clean, logical commits, with a dedicated adaptation commit to ensure a clean build and functional correctness on v6.6.