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iommu/riscv: prefer WSI on IGS=BOTH when wired IRQs are described - #343

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iommu/riscv: prefer WSI on IGS=BOTH when wired IRQs are described#343
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fixed: #342

driver inclusion
category: bugfix
Link: #342
Reference: https://lkml.org/lkml/2026/5/19/1406

The RISC-V IOMMU spec defines IGS=BOTH as supporting both MSI and WSI, with software selecting the path. The DT path already behaves as expected by selecting WSI when wired IRQ resources are described. The ACPI path, however, currently falls back to MSI even when firmware describes wired IRQ resources.

Use firmware-described wired IRQ resources as the trigger to select WSI for IGS=BOTH:

  • DT: "interrupts" present, no "msi-parent"
  • ACPI: DSDT _CRS Interrupt() descriptors (mainline does not yet parse the RIMT Interrupt Wire Array)

When triggered, rewrite igs to IGS_WSI and reuse the existing WSI handling. Keep the existing behaviour otherwise.

Fixes: d5f88ac ("iommu/riscv: Add support for platform msi")

clementleger and others added 30 commits July 1, 2026 10:17
@clementleger @sterling-teng
RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
1b82795 
mainline inclusion
from mainline-6.16-rc1
commit bb053f8
category: feature
bugzilla: RVCK-Project#239

--------------------------------

SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate
misaligned load/store exceptions. Save and restore it during CPU
load/put.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20250523101932.1594077-15-cleger@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@andreas-schwab @sterling-teng
riscv: traps_misaligned: properly sign extend value in misaligned loa…
0884cfd 
…d handler

mainline inclusion
from mainline-6.16-rc7
commit b351018
category: feature
bugzilla: RVCK-Project#229

--------------------------------

Add missing cast to signed long.

Signed-off-by: Andreas Schwab <schwab@suse.de>
Fixes: 956d705 ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
Alexandre Ghiti @sterling-teng
riscv: Fix typo EXRACT -> EXTRACT
e7a667b 
mainline inclusion
from mainline-6.17-rc7
commit 932131f
category: feature
bugzilla: RVCK-Project#239

--------------------------------

Simply fix a typo.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20250620-dev-alex-insn_duplicate_v5_manual-v5-1-d865dc9ad180@rivosinc.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
Alexandre Ghiti @sterling-teng
riscv: Strengthen duplicate and inconsistent definition of RV_X()
cd3159d 
mainline inclusion
from mainline-6.17-rc7
commit 833bbb0
category: feature
bugzilla: RVCK-Project#239

--------------------------------

RV_X() macro is defined in two different ways which is error prone.

So harmonize its first definition and add another macro RV_X_MASK() for
the second one.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250620-dev-alex-insn_duplicate_v5_manual-v5-2-d865dc9ad180@rivosinc.com
[pjw@kernel.org: upcase the macro name to conform with previous practice]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
Alexandre Ghiti @sterling-teng
riscv: Move all duplicate insn parsing macros into asm/insn.h
3c0a19c 
mainline inclusion
from mainline-6.17-rc7
commit a601732
category: feature
bugzilla: RVCK-Project#239

--------------------------------

kernel/traps_misaligned.c and kvm/vcpu_insn.c define the same macros to
extract information from the instructions.

Let's move the definitions into asm/insn.h to avoid this duplication.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20250620-dev-alex-insn_duplicate_v5_manual-v5-3-d865dc9ad180@rivosinc.com
[pjw@kernel.org: updated to apply]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@covanam @sterling-teng
Revert "riscv: misaligned: fix sleeping function called during misali…
50871a1 
…gned access handling"

mainline inclusion
from mainline-6.16-rc4
commit 2f73c62
category: feature
bugzilla: RVCK-Project#239

--------------------------------

This reverts commit 61a74ad ("riscv: misaligned: fix sleeping function
called during misaligned access handling"). The commit addresses a sleeping
in atomic context problem, but it is not the correct fix as explained by
Clément:

"Using nofault would lead to failure to read from user memory that is paged
out for instance. This is not really acceptable, we should handle user
misaligned access even at an address that would generate a page fault."

This bug has been properly fixed by commit 453805f ("riscv:
misaligned: enable IRQs while handling misaligned accesses").

Revert this improper fix.

Link: https://lore.kernel.org/linux-riscv/b779beed-e44e-4a5e-9551-4647682b0d21@rivosinc.com/
Signed-off-by: Nam Cao <namcao@linutronix.de>
Cc: stable@vger.kernel.org
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Fixes: 61a74ad ("riscv: misaligned: fix sleeping function called during misaligned access handling")
Link: https://lore.kernel.org/r/20250620110939.1642735-1-namcao@linutronix.de
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
jichuan Feng @sterling-teng
riscv: k1: add MUSE Pi Pro device tree
246828b 
category: feature
bugzilla: RVCK-Project#248

--------------------------------

Add the device tree for the Spacemit MUSE Pi Pro board.
Enable the basic peripherals and board-specific devices used
on the platform.

Signed-off-by: jichuan Feng <jichuan.or@isrc.iscas.ac.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
jichuan Feng @sterling-teng
riscv: k1: add MUSE Pi device tree
b62b947 
category: feature
bugzilla: RVCK-Project#248

--------------------------------

Add the device tree for the Spacemit MUSE Pi board.
Enable the basic peripherals and board-specific devices used
on the platform.

Signed-off-by: jichuan Feng <jichuan.or@isrc.iscas.ac.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
jichuan Feng @sterling-teng
riscv: k1: add Milk-V Jupiter device tree
85dc6ec 
category: feature
bugzilla: RVCK-Project#248

--------------------------------

Add the device tree for the Milk-V Jupiter board.
Enable the basic peripherals and board-specific devices used
on the platform.

Signed-off-by: jichuan Feng <jichuan.or@isrc.iscas.ac.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
jichuan Feng @sterling-teng
riscv: k1: add OrangePi RV2 device tree
2539573 
category: feature
bugzilla: RVCK-Project#248

--------------------------------

Add the device tree for the Spacemit OrangePi RV2 board.
Enable the basic peripherals and board-specific devices used
on the platform.

Signed-off-by: jichuan Feng <jichuan.or@isrc.iscas.ac.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
ZhenXing Zhu @sterling-teng
Revert "audio: th1520: to support tdm/spdif feature"
66c5c97 
dist inclusion
category: cleanup
Link: RVCK-Project#249

--------------------------------

This reverts commit 8297afc.

Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
ZhenXing Zhu @sterling-teng
Revert "dts: audio: to support i2s-8ch feature"
b5c4244 
dist inclusion
category: cleanup
Link: RVCK-Project#249

--------------------------------

This reverts commit a7bf54d.

Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
ZhenXing Zhu @sterling-teng
Revert "audio: th1520: add tdm driver for XuanTie TH1520 SoC"
d05c5d3 
dist inclusion
category: cleanup
Link: RVCK-Project#249

--------------------------------

This reverts commit 44dc885.

Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
ZhenXing Zhu @sterling-teng
Revert "i2s: add i2s driver for XuanTie TH1520 SoC"
fdb252b 
dist inclusion
category: cleanup
Link: RVCK-Project#249

---------------------------------

This reverts commit d0c9470.

Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@rafaeljw @sterling-teng
ACPI: property: Support using strings in reference properties
dfd5c8a 
mainline inclusion
from mainline-6.7-rc3
commit 9880702
category: feature
bugzilla: RVCK-Project#243

--------------------------------

In order to allow referencing data nodes directly, which is not possible
currently, add support for representing references in device properties
as strings (relative or absolute name paths).  For example, after this
change, the "mipi-img-flash-leds" property in the ASL snippet below will
be treated as a proper reference to the LED0 object under LEDD.

 Package ()
 {
     "mipi-img-flash-leds",  "\\_SB.PCI0.I2C2.LEDD.LED0",
 }

 Device (LEDD)
 {
     Name (_DSD, Package ()  // _DSD: Device-Specific Data
     {
         ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), /* Hierarchical Data Extension */,
         Package ()
         {
             Package ()
             {
                 "mipi-img-flash-led-0",
                 "LED0",
             }
         },
     })
     Name (LED0, Package ()  // _DSD: Device-Specific Data
     {
         ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties */,
         Package ()
         {
             Package ()
             {
                 "mipi-img-max-current",
                 1000000,
             }
         }
     })
 }

Also remove the mechanism allowing data nodes to be referenced
indirectly, with the help of an object reference pointing to the
"ancestor" device and a path relative to it (this mechanism is not
expected to be in use in any production platform firmware in the field).

Note that this change allows also using strings for referencing device
objects, in addition to object references that have been supported
already.

While at it, add pr_fmt() macro to prefix printouts and update
copyright.

Co-developed-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Tested-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
Sakari Ailus @sterling-teng
Documentation: ACPI: Use all-string data node references
3838707 
mainline inclusion
from mainline-6.15-rc2
commit 6db0261
category: feature
bugzilla: RVCK-Project#243

--------------------------------

Document that references to data nodes shall use string-only references
instead of a device reference and a succession of the first package
entries of hierarchical data node references.

Fixes: 9880702 ("ACPI: property: Support using strings in reference properties")
Cc: 6.8+ <stable@vger.kernel.org> # 6.8+
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Link: https://patch.msgid.link/20250409084738.3657079-1-sakari.ailus@linux.intel.com
[ rjw: Clarifying edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
Tanzir Hasan @sterling-teng
kernel.h: removed REPEAT_BYTE from kernel.h
60cfe85 
mainline inclusion
from mainline-6.8-rc3
commit 66a5c40
category: feature
bugzilla: RVCK-Project#243

--------------------------------

This patch creates wordpart.h and includes it in asm/word-at-a-time.h
for all architectures. WORD_AT_A_TIME_CONSTANTS depends on kernel.h
because of REPEAT_BYTE. Moving this to another header and including it
where necessary allows us to not include the bloated kernel.h. Making
this implicit dependency on REPEAT_BYTE explicit allows for later
improvements in the lib/string.c inclusion list.

Suggested-by: Al Viro <viro@zeniv.linux.org.uk>
Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Tanzir Hasan <tanzirh@google.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20231226-libstringheader-v6-1-80aa08c7652c@google.com
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
Tanzir Hasan @sterling-teng
lib/string: shrink lib/string.i via IWYU
2d645e0 
mainline inclusion
from mainline-6.8-rc3
commit 38b9baf
category: feature
bugzilla: RVCK-Project#243

--------------------------------

This diff uses an open source tool include-what-you-use (IWYU) to modify
the include list, changing indirect includes to direct includes. IWYU is
implemented using the IWYUScripts github repository which is a tool that
is currently undergoing development. These changes seek to improve build
times.

This change to lib/string.c resulted in a preprocessed size of
lib/string.i from 26371 lines to 5321 lines (-80%) for the x86
defconfig.

Link: https://github.com/ClangBuiltLinux/IWYUScripts
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Tanzir Hasan <tanzirh@google.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20231226-libstringheader-v6-2-80aa08c7652c@google.com
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@andy-shev @sterling-teng
driver core: Split devres APIs to device/devres.h
1e67996 
mainline inclusion
from mainline-6.14-rc5
commit a21cad9
category: feature
bugzilla: RVCK-Project#243

--------------------------------

device.h is a huge header which is hard to follow and easy to miss
something. Improve that by splitting devres APIs to device/devres.h.

In particular this helps to speedup the build of the code that includes
device.h solely for a devres APIs.

While at it, cast the error pointers to __iomem using IOMEM_ERR_PTR()
and fix sparse warnings.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@avpatel @sterling-teng
dt-bindings: mailbox: Add bindings for RPMI shared memory transport
c376848 
mainline inclusion
from mainline-6.17
commit 492263f
category: feature
bugzilla: RVCK-Project#243

--------------------------------

Add device tree bindings for the common RISC-V Platform Management
Interface (RPMI) shared memory transport as a mailbox controller.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-2-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@avpatel @sterling-teng
dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension
97c1f22 
mainline inclusion
from mainline-6.17
commit 581b4da
category: feature
bugzilla: RVCK-Project#243

--------------------------------

Add device tree bindings for the RISC-V SBI Message Proxy (MPXY)
extension as a mailbox controller.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-3-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@avpatel @sterling-teng
RISC-V: Add defines for the SBI message proxy extension
f159067 
mainline inclusion
from mainline-6.17
commit 508da38
category: feature
bugzilla: RVCK-Project#229

--------------------------------

Add defines for the new SBI message proxy extension which is part
of the SBI v3.0 specification.

Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20250818040920.272664-4-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@avpatel @sterling-teng
mailbox: Add common header for RPMI messages sent via mailbox
561c318 
mainline inclusion
from mainline-6.17
commit 340974c
category: feature
bugzilla: RVCK-Project#243

--------------------------------

The RPMI based mailbox controller drivers and mailbox clients need to
share defines related to RPMI messages over mailbox interface so add
a common header for this purpose.

Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20250818040920.272664-5-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@avpatel @sterling-teng
byteorder: Add memcpy_to_le32() and memcpy_from_le32()
488d86b 
mainline inclusion
from mainline-6.17
commit 6f01c24
category: feature
bugzilla: RVCK-Project#243

--------------------------------

Add common memcpy APIs for copying u32 array to/from __le32 array.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-7-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@avpatel @sterling-teng
mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver
5c41e7d 
mainline inclusion
from mainline-6.17
commit bf3022a
category: feature
bugzilla: RVCK-Project#243

--------------------------------

Add a mailbox controller driver for the new SBI message proxy extension
which is part of the SBI v3.0 specification.

Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20250818040920.272664-8-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@avpatel @sterling-teng
dt-bindings: clock: Add RPMI clock service message proxy bindings
3db06e9 
mainline inclusion
from mainline-6.17
commit 54e184f
category: feature
bugzilla: RVCK-Project#243

--------------------------------

Add device tree bindings for the RPMI clock service group based
message proxy implemented by the SBI implementation (machine mode
firmware or hypervisor).

The RPMI clock service group is defined by the RISC-V platform
management interface (RPMI) specification.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20250818040920.272664-9-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@avpatel @sterling-teng
dt-bindings: clock: Add RPMI clock service controller bindings
eab5d36 
mainline inclusion
from mainline-6.17
commit b385830
category: feature
bugzilla: RVCK-Project#243

--------------------------------

Add device tree bindings for the RPMI clock service group based
controller for the supervisor software.

The RPMI clock service group is defined by the RISC-V platform
management interface (RPMI) specification.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-10-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@pathakraul @sterling-teng
clk: Add clock driver for the RISC-V RPMI clock service group
a99bb57 
mainline inclusion
from mainline-6.17
commit 5ba9f52
category: feature
bugzilla: RVCK-Project#243

--------------------------------

The RPMI specification defines a clock service group which can be
accessed via SBI MPXY extension or dedicated S-mode RPMI transport.

Add mailbox client based clock driver for the RISC-V RPMI clock
service group.

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Co-developed-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Link: https://lore.kernel.org/r/20250818040920.272664-11-apatel@ventanamicro.com
[pjw@kernel.org: converted rpmi_clkrate_u64 macro to a function; replaced bare constant with a macro]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@avpatel @sterling-teng
dt-bindings: Add RPMI system MSI message proxy bindings
389243c 
mainline inclusion
from mainline-6.17
commit a72ab25
category: feature
bugzilla: RVCK-Project#243

--------------------------------

Add device tree bindings for the RPMI system MSI service group
based message proxy implemented by the SBI implementation (machine
mode firmware or hypervisor).

The RPMI system MSI service group is defined by the RISC-V
platform management interface (RPMI) specification.

Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-12-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
@avpatel @sterling-teng
dt-bindings: Add RPMI system MSI interrupt controller bindings
717f017 
mainline inclusion
from mainline-6.17
commit 3e6cf38
category: feature
bugzilla: RVCK-Project#243

--------------------------------

Add device tree bindings for the RPMI system MSI service group
based interrupt controller for the supervisor software.

The RPMI system MSI service group is defined by the RISC-V
platform management interface (RPMI) specification.

Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-13-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
lyctw and others added 27 commits July 1, 2026 14:17
@lyctw @uestc-gr
dt-bindings: riscv: Add Andes PMU extension description
9d54460 
mainline inclusion
from mainline-6.9-rc1
commit 61609bf
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-9-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@AndybnACT @uestc-gr
dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description
f54e55b 
mainline inclusion
from mainline-6.10-rc2
commit 037df29
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240510-zve-detection-v5-4-0711bdd26c12@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@clementleger @uestc-gr
dt-bindings: riscv: add Zimop ISA extension description
0c11e35 
mainline inclusion
from mainline-6.10-rc6
commit a57b68b
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zimop (May-Be-Operations) ISA extension which
was ratified in commit 58220614a5f of the riscv-isa-manual.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240619113529.676940-2-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@clementleger @uestc-gr
dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description
f8dbada 
mainline inclusion
from mainline-6.10-rc6
commit e9f9946
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for Zca, Zcf, Zcd and Zcb extensions which are part the
Zc* standard extensions for code size reduction. Additional validation
rules are added since Zcb depends on Zca, Zcf, depends on Zca and F, Zcd
depends on Zca and D and finally, Zcf can not be present on rv64.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240619113529.676940-7-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@clementleger @uestc-gr
dt-bindings: riscv: add Zcmop ISA extension description
22ec210 
mainline inclusion
from mainline-6.10-rc6
commit 700556a
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zcmop (Compressed May-Be-Operations) ISA
extension which was ratified in commit c732a4f39a4c ("Zcmop is
ratified/1.0") of the riscv-isa-manual.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240619113529.676940-13-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@inochisa @uestc-gr
dt-bindings: riscv: add bfloat16 ISA extension description
0eeec58 
mainline inclusion
from mainline-6.14
commit 35bc188
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250213003849.147358-2-inochiama@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Andrew Jones @uestc-gr
dt-bindings: riscv: Add Zawrs ISA extension description
97b5cc4 
mainline inclusion
from mainline-6.10
commit 6d58528
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zawrs (Wait-on-Reservation-Set) ISA extension
which was ratified in commit 98918c844281 of riscv-isa-manual.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240426100820.14762-10-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Alexandre Ghiti @uestc-gr
dt-bindings: riscv: Add Svvptc ISA extension description
a2e78c0 
mainline inclusion
from mainline-6.11
commit d25599b
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Svvptc ISA extension which was ratified recently.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240717060125.139416-3-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@SiFiveHolland @uestc-gr
dt-bindings: riscv: Add pointer masking ISA extensions
7dd6d22 
mainline inclusion
from mainline-6.12-rc5
commit 8727163
category: feature
bugzilla: RVCK-Project#304

--------------------------------

The RISC-V Pointer Masking specification defines three extensions:
Smmpm, Smnpm, and Ssnpm. Document the behavior of these extensions as
following the ratified version 1.0 of the specification.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20241016202814.4061541-2-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
Alexandre Ghiti @uestc-gr
dt-bindings: riscv: Add Zabha ISA extension description
6070dd9 
mainline inclusion
from mainline-6.12
commit 51624dd
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zabha ISA extension which was ratified in April
2024.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241103145153.105097-5-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@clementleger @uestc-gr
dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description
b06939d 
mainline inclusion
from mainline-6.14
commit a65e0f6
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add description for the Zaamo and Zalrsc ISA extension[1].

Link: https://github.com/riscv/riscv-zaamo-zalrsc [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240619153913.867263-2-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@ConchuOD @uestc-gr
dt-bindings: riscv: d requires f
9a0e1f4 
mainline inclusion
from mainline-6.15-rc1
commit 534d813
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Per the specifications, the d extension for double-precision floating
point operations depends on the f extension for single-precision floating
point. Add that requirement to the bindings. This differs from the
Linux implementation, where single-precious only is not supported.

Reviewed-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250312-perpetual-daunting-ad489c9a857a@spud
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@ConchuOD @uestc-gr
dt-bindings: riscv: add vector sub-extension dependencies
a6e8bcd 
mainline inclusion
from mainline-6.15-rc1
commit e9f1d61
category: feature
bugzilla: RVCK-Project#304

--------------------------------
Section 33.18.2. Zve*: Vector Extensions for Embedded Processors
in [1] says:
| The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends
| on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension

| The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend
| upon the F extension

| The Zve64d extension depends upon the D extension

Apply these rules to the bindings to help prevent invalid combinations.

Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09 [1]
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250312-banking-crestless-58f3259a5018@spud
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@ConchuOD @uestc-gr
dt-bindings: riscv: document vector crypto requirements
cd08520 
mainline inclusion
from mainline-6.15-rc1
commit a0d8572
category: feature
bugzilla: RVCK-Project#304

--------------------------------

The Unpriv spec states:
| The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the
| composite extensions Zvkn, Zvknc, Zvkng, and Zvksc-- require a Zve64x
| base, or application ("V") base Vector Extension. All of the other
| Vector Crypto Extensions can be built on any embedded (Zve*) or
| application ("V") base Vector Extension.

Enforce the minimum requirement via schema.

Link: https://github.com/riscv/riscv-isa-manual/blob/main/src/vector-crypto.adoc#extensions-overview
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250312-flask-relay-b36ee622b2c8@spud
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@wpcwzy @uestc-gr
dt-bindings: riscv: add Zilsd and Zclsd extension descriptions
1f10d2b 
mainline inclusion
from mainline-6.19-rc2
commit 4115155
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add descriptions for the Zilsd (Load/Store pair instructions) and
Zclsd (Compressed Load/Store pair instructions) ISA extensions
which were ratified in commit f88abf1 ("Integrating load/store
pair for RV32 with the main manual") of the riscv-isa-manual.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20250826162939.1494021-2-pincheng.plct@isrc.iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@wpcwzy @uestc-gr
riscv: add ISA extension parsing for Zilsd and Zclsd
dd73223 
mainline inclusion
from mainline-6.19-rc2
commit 3f0cbfb
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Add parsing for Zilsd and Zclsd ISA extensions which were ratified in
commit f88abf1 ("Integrating load/store pair for RV32 with the
main manual") of the riscv-isa-manual.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Link: https://patch.msgid.link/20250826162939.1494021-3-pincheng.plct@isrc.iscas.ac.cn
[pjw@kernel.org: cleaned up checkpatch issues, whitespace; updated to apply]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@wpcwzy @uestc-gr
riscv: hwprobe: export Zilsd and Zclsd ISA extensions
b3f0af3 
mainline inclusion
from mainline-6.19-rc2
commit 6118ebe
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Export Zilsd and Zclsd ISA extensions through hwprobe.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Link: https://patch.msgid.link/20250826162939.1494021-4-pincheng.plct@isrc.iscas.ac.cn
[pjw@kernel.org: fixed whitespace; updated to apply]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@wpcwzy @uestc-gr
riscv: KVM: allow Zilsd and Zclsd extensions for Guest/VM
0b542d5 
mainline inclusion
from mainline-6.19-rc2
commit f326e84
category: feature
bugzilla: RVCK-Project#304

--------------------------------

Extend the KVM ISA extension ONE_REG interface to allow KVM user space
to detect and enable Zilsd and Zclsd extensions for Guest/VM.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250826162939.1494021-5-pincheng.plct@isrc.iscas.ac.cn
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
@wpcwzy @uestc-gr
KVM: riscv: selftests: add Zilsd and Zclsd extension to get-reg-list …
381f169 
…test

mainline inclusion
from mainline-6.19-rc2
commit ab2a7b7
category: feature
bugzilla: RVCK-Project#304

--------------------------------

The KVM RISC-V allows Zilsd and Zclsd extensions for Guest/VM so add
this extension to get-reg-list test.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250826162939.1494021-6-pincheng.plct@isrc.iscas.ac.cn
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
heyilin @GooTal
PERF: Update LRW PMU Event Encoding
9b1a080 
driver inclusion
category other
Link: RVCK-Project#315

-------------------------------------------------

Correct register names, descriptions, and definitions
in JSON config files to match the latest hardware spec;
remove deprecated registers and obsolete files.
Metadata/documentation changes only. No functional
logic modified. Ensure downstream tools handle the
removed file and updated definitions.

Signed-off-by: heyilin <he.yilin@zte.com.cn>
Signed-off-by: liuqingtao <liu.qingtao2@zte.com.cn>
@sterling-teng
Merge pull request RVCK-Project#316 from zte-riscv/pr-core-pmu-num-fix
3eb7800 
PERF: Update LRW PMU Event Encoding
@cp0613 @unicornx
riscv: vdso_cfi: Add clean rule for copied sources
493634c 
mainline inclusion
from mainline-v7.1-rc1
commit 382cf7b ("riscv: vdso_cfi: Add clean rule for copied sources")
category: bugfix
bugzilla: RVCK-Project#328

--------------------------------

When building VDSO with CFI support, source files are copied from the main
VDSO directory to the CFI build directory as part of the build process.
However, these copied source files were not removed during 'make clean',
leaving temporary files in the build directory.

Add the clean-files variable to ensure that these copied .c and .S files
are properly cleaned up. The notdir() function is used to strip the path
prefix, as clean-files expects relative file names without directory
components.

This ensures the build directory is left in a clean state after make clean.

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
Link: https://patch.msgid.link/20260320021850.1877-2-cp0613@linux.alibaba.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
bailu @GooTal
iommu/riscv: add dma_wmb before cmpxchg_relaxed
a71ca51 
driver inclusion
category: bugfix
Link: RVCK-Project#308

--------------------------------

When using NVMe for PCIe peripherals on an RV multi-core CPU with IOMMU
enabled, the command `fio --filename=/dev/nvme0n1 --ioengine=libaio
--direct=1 --iodepth=256 --numjobs=8 --group_reporting=1 --bs=1M
--time_based=1 --runtime=2 --rw=read --name=test_read_8 --thread=1`
resulted a fault 15 exception during IOMMU testing.

When multiple cores modify iommu page talbe simultaneously, executing
riscv_iommu_map_pages or riscv_iommu_pte_alloc, an out-of-order iommu
page table clearing problem can occur due to a memory barrier missing.
It caused PTE being incorrectly cleared.

Setting dma_wmb ensures that all previous DMA write operations have
been completed before cmpxchg_relaxed.

This issue is relatively rare and may only occur during stress testing.

Signed-off-by: bailu <bai.lu5@zte.com.cn>
Signed-off-by: liuqingtao <liu.qingtao2@zte.com.cn>
@sterling-teng
Merge pull request RVCK-Project#309 from zte-riscv/pr-iommu-dma_wmb
6e2f72b 
iommu/riscv: add dma_wmb before cmpxchg_relaxed
@sterling-teng
Merge pull request RVCK-Project#305 from uestc-gr/Zilsd
cc8d212 
Add Zilsd/Zclsd support in hwprobe and KVM
@sterling-teng
Merge pull request RVCK-Project#330 from unicornx/dev-backport-382cf7b
6f2837b 
riscv: vdso_cfi: Add clean rule for copied sources
@fangyu0809 Li Hongbin
iommu/riscv: prefer WSI on IGS=BOTH when wired IRQs are described
132f2dd 
driver inclusion
category: bugfix
Link: RVCK-Project#342
Reference: https://lkml.org/lkml/2026/5/19/1406

--------------------------------

The RISC-V IOMMU spec defines IGS=BOTH as supporting both MSI and
WSI, with software selecting the path. The DT path already behaves
as expected by selecting WSI when wired IRQ resources are described.
The ACPI path, however, currently falls back to MSI even when
firmware describes wired IRQ resources.

Use firmware-described wired IRQ resources as the trigger to select
WSI for IGS=BOTH:
  - DT: "interrupts" present, no "msi-parent"
  - ACPI: DSDT _CRS Interrupt() descriptors
    (mainline does not yet parse the RIMT Interrupt Wire Array)

When triggered, rewrite igs to IGS_WSI and reuse the existing WSI
handling. Keep the existing behaviour otherwise.

Fixes: d5f88ac ("iommu/riscv: Add support for platform msi")
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Signed-off-by: Li Hongbin <lihongbin@lanxincomputing.com>
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github-actions Bot commented Jul 22, 2026 •
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/29907454871

参数解析结果
args value
repository RVCK-Project/rvck
head ref pull/343/head
base ref rvck-6.6
LAVA repo RVCK-Project/lavaci
LAVA hardware ['qemu']
LAVA Testcase path lava-testcases/common-test/ltp/ltp.yaml
need run job kunit-test,kernel-build,check-patch,lava-trigger

测试完成

详细结果:
check result
kunit-test success
kernel-build success
check-patch failure
lava-trigger-qemu success
lava-trigger-sg2042 skipped
lava-trigger-k1 skipped
lava-trigger-lpi4a skipped

Kunit Test Result

[09:23:28] Testing complete. Ran 482 tests: passed: 465, skipped: 17

Kernel Build Result

Check Patch Result
Total Errors 2
Total Warnings 2

LAVA Check (qemu)

args value
testcase_repo RVCK-Project/lavaci
lava_template lava-job-template/qemu/qemu-ltp.yaml
testcase_path lava-testcases/common-test/ltp/ltp.yaml
kernel_download_url http://10.30.190.110/openEuler-RISC-V/RVCK/OERV-RVCI/RVCK-Project/rvck/343_29907454871_1/Image
initramfs_download_url http://10.30.190.110/openEuler-RISC-V/RVCK/OERV-RVCI/RVCK-Project/rvck/343_29907454871_1/initramfs.img
rootfs_download_url https://fast-mirror.isrc.ac.cn/openeuler-sig-riscv/openEuler-RISC-V/RVCK/openEuler24.03-LTS-SP1/openeuler-rootfs.img.zst
testcase_ref main
testitem_name RVCK-Project_rvck_pull_request_target_343__common-test_qemu

result: Lava check done!

@unicornx unicornx added the LanxinComputing 蓝芯算力 label Jul 22, 2026
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IOMMU ACPI路径下MSI中断/线中断选择问题