usb: xhci-pci: Limit VIA VL805 DMA addressing to 36 bits - #349
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usb: xhci-pci: Limit VIA VL805 DMA addressing to 36 bits#349WangJia-UR wants to merge 1513 commits into
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category: feature bugzilla: RVCK-Project#248 -------------------------------- Add the device tree for the Spacemit MUSE Pi Pro board. Enable the basic peripherals and board-specific devices used on the platform. Signed-off-by: jichuan Feng <jichuan.or@isrc.iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
category: feature bugzilla: RVCK-Project#248 -------------------------------- Add the device tree for the Spacemit MUSE Pi board. Enable the basic peripherals and board-specific devices used on the platform. Signed-off-by: jichuan Feng <jichuan.or@isrc.iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
category: feature bugzilla: RVCK-Project#248 -------------------------------- Add the device tree for the Milk-V Jupiter board. Enable the basic peripherals and board-specific devices used on the platform. Signed-off-by: jichuan Feng <jichuan.or@isrc.iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
category: feature bugzilla: RVCK-Project#248 -------------------------------- Add the device tree for the Spacemit OrangePi RV2 board. Enable the basic peripherals and board-specific devices used on the platform. Signed-off-by: jichuan Feng <jichuan.or@isrc.iscas.ac.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
dist inclusion category: cleanup Link: RVCK-Project#249 -------------------------------- This reverts commit 8297afc. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
dist inclusion category: cleanup Link: RVCK-Project#249 -------------------------------- This reverts commit a7bf54d. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
dist inclusion category: cleanup Link: RVCK-Project#249 -------------------------------- This reverts commit 44dc885. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
dist inclusion category: cleanup Link: RVCK-Project#249 --------------------------------- This reverts commit d0c9470. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.7-rc3 commit 9880702 category: feature bugzilla: RVCK-Project#243 -------------------------------- In order to allow referencing data nodes directly, which is not possible currently, add support for representing references in device properties as strings (relative or absolute name paths). For example, after this change, the "mipi-img-flash-leds" property in the ASL snippet below will be treated as a proper reference to the LED0 object under LEDD. Package () { "mipi-img-flash-leds", "\\_SB.PCI0.I2C2.LEDD.LED0", } Device (LEDD) { Name (_DSD, Package () // _DSD: Device-Specific Data { ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), /* Hierarchical Data Extension */, Package () { Package () { "mipi-img-flash-led-0", "LED0", } }, }) Name (LED0, Package () // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties */, Package () { Package () { "mipi-img-max-current", 1000000, } } }) } Also remove the mechanism allowing data nodes to be referenced indirectly, with the help of an object reference pointing to the "ancestor" device and a path relative to it (this mechanism is not expected to be in use in any production platform firmware in the field). Note that this change allows also using strings for referencing device objects, in addition to object references that have been supported already. While at it, add pr_fmt() macro to prefix printouts and update copyright. Co-developed-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Tested-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.15-rc2 commit 6db0261 category: feature bugzilla: RVCK-Project#243 -------------------------------- Document that references to data nodes shall use string-only references instead of a device reference and a succession of the first package entries of hierarchical data node references. Fixes: 9880702 ("ACPI: property: Support using strings in reference properties") Cc: 6.8+ <stable@vger.kernel.org> # 6.8+ Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Link: https://patch.msgid.link/20250409084738.3657079-1-sakari.ailus@linux.intel.com [ rjw: Clarifying edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.8-rc3 commit 66a5c40 category: feature bugzilla: RVCK-Project#243 -------------------------------- This patch creates wordpart.h and includes it in asm/word-at-a-time.h for all architectures. WORD_AT_A_TIME_CONSTANTS depends on kernel.h because of REPEAT_BYTE. Moving this to another header and including it where necessary allows us to not include the bloated kernel.h. Making this implicit dependency on REPEAT_BYTE explicit allows for later improvements in the lib/string.c inclusion list. Suggested-by: Al Viro <viro@zeniv.linux.org.uk> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Tanzir Hasan <tanzirh@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20231226-libstringheader-v6-1-80aa08c7652c@google.com Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.8-rc3 commit 38b9baf category: feature bugzilla: RVCK-Project#243 -------------------------------- This diff uses an open source tool include-what-you-use (IWYU) to modify the include list, changing indirect includes to direct includes. IWYU is implemented using the IWYUScripts github repository which is a tool that is currently undergoing development. These changes seek to improve build times. This change to lib/string.c resulted in a preprocessed size of lib/string.i from 26371 lines to 5321 lines (-80%) for the x86 defconfig. Link: https://github.com/ClangBuiltLinux/IWYUScripts Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Tanzir Hasan <tanzirh@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20231226-libstringheader-v6-2-80aa08c7652c@google.com Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.14-rc5 commit a21cad9 category: feature bugzilla: RVCK-Project#243 -------------------------------- device.h is a huge header which is hard to follow and easy to miss something. Improve that by splitting devres APIs to device/devres.h. In particular this helps to speedup the build of the code that includes device.h solely for a devres APIs. While at it, cast the error pointers to __iomem using IOMEM_ERR_PTR() and fix sparse warnings. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 492263f category: feature bugzilla: RVCK-Project#243 -------------------------------- Add device tree bindings for the common RISC-V Platform Management Interface (RPMI) shared memory transport as a mailbox controller. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-2-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 581b4da category: feature bugzilla: RVCK-Project#243 -------------------------------- Add device tree bindings for the RISC-V SBI Message Proxy (MPXY) extension as a mailbox controller. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-3-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 508da38 category: feature bugzilla: RVCK-Project#229 -------------------------------- Add defines for the new SBI message proxy extension which is part of the SBI v3.0 specification. Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-4-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 340974c category: feature bugzilla: RVCK-Project#243 -------------------------------- The RPMI based mailbox controller drivers and mailbox clients need to share defines related to RPMI messages over mailbox interface so add a common header for this purpose. Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-5-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 6f01c24 category: feature bugzilla: RVCK-Project#243 -------------------------------- Add common memcpy APIs for copying u32 array to/from __le32 array. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-7-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit bf3022a category: feature bugzilla: RVCK-Project#243 -------------------------------- Add a mailbox controller driver for the new SBI message proxy extension which is part of the SBI v3.0 specification. Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-8-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 54e184f category: feature bugzilla: RVCK-Project#243 -------------------------------- Add device tree bindings for the RPMI clock service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20250818040920.272664-9-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit b385830 category: feature bugzilla: RVCK-Project#243 -------------------------------- Add device tree bindings for the RPMI clock service group based controller for the supervisor software. The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-10-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 5ba9f52 category: feature bugzilla: RVCK-Project#243 -------------------------------- The RPMI specification defines a clock service group which can be accessed via SBI MPXY extension or dedicated S-mode RPMI transport. Add mailbox client based clock driver for the RISC-V RPMI clock service group. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Co-developed-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-11-apatel@ventanamicro.com [pjw@kernel.org: converted rpmi_clkrate_u64 macro to a function; replaced bare constant with a macro] Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit a72ab25 category: feature bugzilla: RVCK-Project#243 -------------------------------- Add device tree bindings for the RPMI system MSI service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI system MSI service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-12-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 3e6cf38 category: feature bugzilla: RVCK-Project#243 -------------------------------- Add device tree bindings for the RPMI system MSI service group based interrupt controller for the supervisor software. The RPMI system MSI service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-13-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit aa43953 category: feature bugzilla: RVCK-Project#243 -------------------------------- The RPMI specification defines a system MSI service group which allows application processors to receive MSIs upon system events such as graceful shutdown/reboot request, CPU hotplug event, memory hotplug event, etc. Add an irqchip driver for the RISC-V RPMI system MSI service group to directly receive system MSIs in Linux kernel. Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-14-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
…nargs_prop mainline inclusion from mainline-6.17 commit e121be7 category: feature bugzilla: RVCK-Project#243 -------------------------------- Currently, acpi_fwnode_get_reference_args() delegates to the internal function __acpi_node_get_property_reference() to retrieve property references. However, this function does not handle the nargs_prop (cells property) parameter, and instead expects the number of arguments (nargs) to be known or hardcoded. As a result, when fwnode_property_get_reference_args() is used with a valid nargs_prop, the ACPI backend ignores it, whereas the Device Tree (DT) backend uses the #*-cells property from the reference node to determine the number of arguments dynamically. To support the nargs_prop in ACPI, refactor the code as follows: - Move the implementation from __acpi_node_get_property_reference() into acpi_fwnode_get_reference_args(). - Update __acpi_node_get_property_reference() to call the (now updated) acpi_fwnode_get_reference_args() passing NULL as nargs_prop to keep the behavior of __acpi_node_get_property_reference() intact. Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-15-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 159c86f category: feature bugzilla: RVCK-Project#243 -------------------------------- Currently, ACPI does not support the use of a nargs_prop (e.g., associated with a reference in fwnode_property_get_reference_args(). Instead, ACPI expects the number of arguments (nargs) to be explicitly passed or known. This behavior diverges from Open Firmware (OF), which allows the use of a #*-cells property in the referenced node to determine the number of arguments. Since fwnode_property_get_reference_args() is a common interface used across both OF and ACPI firmware paradigms, it is desirable to have a unified calling convention that works seamlessly for both. Add the support for ACPI to parse a nargs_prop from the referenced fwnode, aligning its behavior with the OF backend. This allows drivers and subsystems using fwnode_property_get_reference_args() to work in a firmware-agnostic way without having to hardcode or special-case argument counts for ACPI. Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-16-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 4215d1c category: feature bugzilla: RVCK-Project#243 -------------------------------- The RPMI System MSI interrupt controller (just like PLIC and APLIC) needs to probed prior to devices like GED which use interrupts provided by it. Also, it has dependency on the SBI MPXY mailbox device. Add HIDs of RPMI System MSI and SBI MPXY mailbox devices to the honor list so that those dependencies are handled. Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-17-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 694b2ef category: feature bugzilla: RVCK-Project#243 -------------------------------- Currently, the interrupt controller list is created without any order. Create the list sorted with the GSI base of the interrupt controllers. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-18-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 4d185fd category: feature bugzilla: RVCK-Project#243 -------------------------------- Some RISC-V interrupt controllers like RPMI based system MSI interrupt controllers do not have MADT entry defined. These interrupt controllers exist only in the namespace. ACPI spec defines _GSB method to get the GSI base of the interrupt controller, However, there is no such standard method to get the GSI range. To support such interrupt controllers, set the GSI range of such interrupt controllers to non-overlapping range and provide API for interrupt controller driver to update it with proper value. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-19-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.10 commit 6d58528 category: feature bugzilla: RVCK-Project#304 -------------------------------- Add description for the Zawrs (Wait-on-Reservation-Set) ISA extension which was ratified in commit 98918c844281 of riscv-isa-manual. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240426100820.14762-10-ajones@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.11 commit d25599b category: feature bugzilla: RVCK-Project#304 -------------------------------- Add description for the Svvptc ISA extension which was ratified recently. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240717060125.139416-3-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.12-rc5 commit 8727163 category: feature bugzilla: RVCK-Project#304 -------------------------------- The RISC-V Pointer Masking specification defines three extensions: Smmpm, Smnpm, and Ssnpm. Document the behavior of these extensions as following the ratified version 1.0 of the specification. Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20241016202814.4061541-2-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.12 commit 51624dd category: feature bugzilla: RVCK-Project#304 -------------------------------- Add description for the Zabha ISA extension which was ratified in April 2024. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Andrea Parri <parri.andrea@gmail.com> Link: https://lore.kernel.org/r/20241103145153.105097-5-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.14 commit a65e0f6 category: feature bugzilla: RVCK-Project#304 -------------------------------- Add description for the Zaamo and Zalrsc ISA extension[1]. Link: https://github.com/riscv/riscv-zaamo-zalrsc [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240619153913.867263-2-cleger@rivosinc.com Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.15-rc1 commit 534d813 category: feature bugzilla: RVCK-Project#304 -------------------------------- Per the specifications, the d extension for double-precision floating point operations depends on the f extension for single-precision floating point. Add that requirement to the bindings. This differs from the Linux implementation, where single-precious only is not supported. Reviewed-by: Clément Léger <cleger@rivosinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250312-perpetual-daunting-ad489c9a857a@spud Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.15-rc1 commit e9f1d61 category: feature bugzilla: RVCK-Project#304 -------------------------------- Section 33.18.2. Zve*: Vector Extensions for Embedded Processors in [1] says: | The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends | on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension | The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend | upon the F extension | The Zve64d extension depends upon the D extension Apply these rules to the bindings to help prevent invalid combinations. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09 [1] Reviewed-by: Clément Léger <cleger@rivosinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250312-banking-crestless-58f3259a5018@spud Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.15-rc1 commit a0d8572 category: feature bugzilla: RVCK-Project#304 -------------------------------- The Unpriv spec states: | The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the | composite extensions Zvkn, Zvknc, Zvkng, and Zvksc-- require a Zve64x | base, or application ("V") base Vector Extension. All of the other | Vector Crypto Extensions can be built on any embedded (Zve*) or | application ("V") base Vector Extension. Enforce the minimum requirement via schema. Link: https://github.com/riscv/riscv-isa-manual/blob/main/src/vector-crypto.adoc#extensions-overview Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250312-flask-relay-b36ee622b2c8@spud Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.19-rc2 commit 4115155 category: feature bugzilla: RVCK-Project#304 -------------------------------- Add descriptions for the Zilsd (Load/Store pair instructions) and Zclsd (Compressed Load/Store pair instructions) ISA extensions which were ratified in commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20250826162939.1494021-2-pincheng.plct@isrc.iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.19-rc2 commit 3f0cbfb category: feature bugzilla: RVCK-Project#304 -------------------------------- Add parsing for Zilsd and Zclsd ISA extensions which were ratified in commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Link: https://patch.msgid.link/20250826162939.1494021-3-pincheng.plct@isrc.iscas.ac.cn [pjw@kernel.org: cleaned up checkpatch issues, whitespace; updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.19-rc2 commit 6118ebe category: feature bugzilla: RVCK-Project#304 -------------------------------- Export Zilsd and Zclsd ISA extensions through hwprobe. Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Link: https://patch.msgid.link/20250826162939.1494021-4-pincheng.plct@isrc.iscas.ac.cn [pjw@kernel.org: fixed whitespace; updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-6.19-rc2 commit f326e84 category: feature bugzilla: RVCK-Project#304 -------------------------------- Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zilsd and Zclsd extensions for Guest/VM. Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250826162939.1494021-5-pincheng.plct@isrc.iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
…test mainline inclusion from mainline-6.19-rc2 commit ab2a7b7 category: feature bugzilla: RVCK-Project#304 -------------------------------- The KVM RISC-V allows Zilsd and Zclsd extensions for Guest/VM so add this extension to get-reg-list test. Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250826162939.1494021-6-pincheng.plct@isrc.iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
driver inclusion category other Link: RVCK-Project#315 ------------------------------------------------- Correct register names, descriptions, and definitions in JSON config files to match the latest hardware spec; remove deprecated registers and obsolete files. Metadata/documentation changes only. No functional logic modified. Ensure downstream tools handle the removed file and updated definitions. Signed-off-by: heyilin <he.yilin@zte.com.cn> Signed-off-by: liuqingtao <liu.qingtao2@zte.com.cn>
PERF: Update LRW PMU Event Encoding
mainline inclusion from mainline-v7.1-rc1 commit 382cf7b ("riscv: vdso_cfi: Add clean rule for copied sources") category: bugfix bugzilla: RVCK-Project#328 -------------------------------- When building VDSO with CFI support, source files are copied from the main VDSO directory to the CFI build directory as part of the build process. However, these copied source files were not removed during 'make clean', leaving temporary files in the build directory. Add the clean-files variable to ensure that these copied .c and .S files are properly cleaned up. The notdir() function is used to strip the path prefix, as clean-files expects relative file names without directory components. This ensures the build directory is left in a clean state after make clean. Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Link: https://patch.msgid.link/20260320021850.1877-2-cp0613@linux.alibaba.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
driver inclusion category: bugfix Link: RVCK-Project#308 -------------------------------- When using NVMe for PCIe peripherals on an RV multi-core CPU with IOMMU enabled, the command `fio --filename=/dev/nvme0n1 --ioengine=libaio --direct=1 --iodepth=256 --numjobs=8 --group_reporting=1 --bs=1M --time_based=1 --runtime=2 --rw=read --name=test_read_8 --thread=1` resulted a fault 15 exception during IOMMU testing. When multiple cores modify iommu page talbe simultaneously, executing riscv_iommu_map_pages or riscv_iommu_pte_alloc, an out-of-order iommu page table clearing problem can occur due to a memory barrier missing. It caused PTE being incorrectly cleared. Setting dma_wmb ensures that all previous DMA write operations have been completed before cmpxchg_relaxed. This issue is relatively rare and may only occur during stress testing. Signed-off-by: bailu <bai.lu5@zte.com.cn> Signed-off-by: liuqingtao <liu.qingtao2@zte.com.cn>
iommu/riscv: add dma_wmb before cmpxchg_relaxed
Add Zilsd/Zclsd support in hwprobe and KVM
riscv: vdso_cfi: Add clean rule for copied sources
mainline inclusion from mainline-7.2-rc1 commit 613a2e6 ("usb: dwc3: core: Expose core driver as library") category: feature bugzilla: RVCK-Project#322 And the dwc3_properties structure and the `ignore_clocks_and_resets` flag have been added to glue.h so that generic glue can use them directly without further modifications to the header file. -------------------------------- The DWC3 IP block is handled by three distinct device drivers: XHCI, DWC3 core and a platform specific (optional) DWC3 glue driver. This has resulted in, at least in the case of the Qualcomm glue, the presence of a number of layering violations, where the glue code either can't handle, or has to work around, the fact that core might not probe deterministically. An example of this is that the suspend path should operate slightly different depending on the device operating in host or peripheral mode, and the only way to determine the operating state is to peek into the core's drvdata. The Qualcomm glue driver is expected to make updates in the qscratch register region (the "glue" region) during role switch events, but with the glue and core split using the driver model, there is no reasonable way to introduce listeners for mode changes. Split the dwc3 core platform_driver callbacks and their implementation and export the implementation, to make it possible to deterministically instantiate the dwc3 core as part of the dwc3 glue drivers and to allow flattening of the DeviceTree representation. Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250414-dwc3-refactor-v7-3-f015b358722d@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit e0b6dc0 ("usb: dwc3: add generic driver to support flattened") category: feature bugzilla: RVCK-Project#322 The compatible string has been updated from "spacemit,k1-dwc3" to "spacemit,k3-dwc3" to match the actual hardware platform being adapted. -------------------------------- To support flattened dwc3 dt model and drop the glue layer, introduce the `dwc3-generic` driver. This enables direct binding of the DWC3 core driver and offers an alternative to the existing glue driver `dwc3-of-simple`. Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Signed-off-by: Ze Huang <huang.ze@linux.dev> Link: https://lore.kernel.org/r/20250913-dwc3_generic-v8-2-b50f81f05f95@linux.dev Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
mainline inclusion from mainline-7.2-rc1 commit fe4bc1a ("phy: spacemit: support K1 USB2.0 PHY controller") category: feature bugzilla: RVCK-Project#322 -------------------------------- The SpacemiT K1 SoC includes three USB ports: - One USB2.0 OTG port - One USB2.0 host-only port - One USB3.0 port with an integrated USB2.0 DRD interface Each of these ports is connected to a USB2.0 PHY responsible for USB2 transmission. This commit adds support for the SpacemiT K1 USB2.0 PHY, which is compliant with the USB 2.0 specification and supports both 8-bit 60MHz and 16-bit 30MHz parallel interfaces. Signed-off-by: Ze Huang <huang.ze@linux.dev> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com> Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-2-7cf9ea2477a1@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
riscv inclusion category: feature bugzilla: RVCK-Project#322 -------------------------------- Add the SpacemiT K3 USB3 combo PHY driver. On K3 the PCIe/USB subsystem provides three single-lane PIPE3 PHYs (PHY2/3/4) shared between PCIe Port C/D and USB3 Port B/C/D. Lane ownership is selected through the APMU PMUA_PCIE_SUBSYS_MGMT register: the driver acquires the syscon-apmu regmap, disables PCIe-A x8 mode and switches the requested lane to USB before bringing the PHY up, so USB3 operation is only possible when the conflicting PCIe x8 configuration is not in use. Bring-up performs R-calibration trim override (N/P trim) and PLL/PU lock polling via the HSIO APB spare registers, and exposes the standard generic-phy init/exit/power and set_speed operations for the xHCI/dwc3 stack. The driver also registers a Type-C orientation switch/mux so the combo PHY can follow cable orientation on Type-C ports. Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
riscv inclusion category: feature bugzilla: RVCK-Project#322 -------------------------------- Add the K3 USB3 controller and combo PHY nodes to k3.dtsi and enable them on the com260 board, wiring up the usb3_portb controller, its USB2/USB3 PHYs and the on-board VL817 hub. Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
USB: spacemit-k3: Add Spacemit K3 USB host controller support
mainline inclusion from mainline-v7.2-rc5 commit 1fc50f1 category: bugfix bugzilla: RVCK-Project#347 -------------------------------- The VIA VL805/806 xHCI controller advertises AC64, but fails to handle DMA addresses at or above 0x1000000000. On systems with large amounts of RAM, this can cause USB device failures when the controller is given DMA addresses beyond its usable address width. Do not use XHCI_NO_64BIT_SUPPORT for this controller. That quirk clears the cached AC64 capability and limits DMA to 32 bits, causing unnecessary bouncing for addresses between 4GiB and 64GiB and hiding the controller's real AC64 capability from code that may need to distinguish register access width from usable DMA address width. Track the usable DMA address width separately from the AC64 capability. Initialize the generic xhci->dma_mask_bits field to 64 and let PCI quirks reduce it for controllers with narrower DMA support. Set VIA VL805/806 to 36 bits so the DMA API only hands it addresses in the range it can handle while keeping HCCPARAMS1.AC64 visible. Cc: stable <stable@kernel.org> Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com> Link: https://patch.msgid.link/20260630-xhci-via-dma-fix-v3-1-690dcb8cf75a@ultrarisc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> [Keep the function-like HCC_64BIT_ADDR() helper used by the 6.6 xHCI code while applying the upstream DMA mask handling.] Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
|
开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/30319647071 参数解析结果
测试完成 详细结果:
Kunit Test Result[01:19:19] Testing complete. Ran 482 tests: passed: 465, skipped: 17
Kernel Build Result
Check Patch Result
LAVA Check (qemu)lava 执行失败. |
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fixed: #347
mainline inclusion
from mainline-v7.2-rc5
commit 1fc50f1
category: bugfix
bugzilla: #347
The VIA VL805/806 xHCI controller advertises AC64, but fails to handle DMA addresses at or above 0x1000000000. On systems with large amounts of RAM, this can cause USB device failures when the controller is given DMA addresses beyond its usable address width.
Do not use XHCI_NO_64BIT_SUPPORT for this controller. That quirk clears the cached AC64 capability and limits DMA to 32 bits, causing unnecessary bouncing for addresses between 4GiB and 64GiB and hiding the controller's real AC64 capability from code that may need to distinguish register access width from usable DMA address width.
Track the usable DMA address width separately from the AC64 capability. Initialize the generic xhci->dma_mask_bits field to 64 and let PCI quirks reduce it for controllers with narrower DMA support. Set VIA VL805/806 to 36 bits so the DMA API only hands it addresses in the range it can handle while keeping HCCPARAMS1.AC64 visible.
Cc: stable stable@kernel.org
Link: https://patch.msgid.link/20260630-xhci-via-dma-fix-v3-1-690dcb8cf75a@ultrarisc.com
[Keep the function-like HCC_64BIT_ADDR() helper used by the 6.6 xHCI code while applying the upstream DMA mask handling.]
Signed-off-by: Jia Wang wangjia@ultrarisc.com