riscv: backport mainline xtheadvector support - #355
Open
zhuzhenxxx-collab wants to merge 1534 commits into
Open
riscv: backport mainline xtheadvector support #355zhuzhenxxx-collab wants to merge 1534 commits into
zhuzhenxxx-collab wants to merge 1534 commits into
Conversation
mainline inclusion from mainline-6.17 commit 5ba9f52 category: feature bugzilla: RVCK-Project#243 -------------------------------- The RPMI specification defines a clock service group which can be accessed via SBI MPXY extension or dedicated S-mode RPMI transport. Add mailbox client based clock driver for the RISC-V RPMI clock service group. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Co-developed-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-11-apatel@ventanamicro.com [pjw@kernel.org: converted rpmi_clkrate_u64 macro to a function; replaced bare constant with a macro] Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit a72ab25 category: feature bugzilla: RVCK-Project#243 -------------------------------- Add device tree bindings for the RPMI system MSI service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI system MSI service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-12-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 3e6cf38 category: feature bugzilla: RVCK-Project#243 -------------------------------- Add device tree bindings for the RPMI system MSI service group based interrupt controller for the supervisor software. The RPMI system MSI service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-13-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit aa43953 category: feature bugzilla: RVCK-Project#243 -------------------------------- The RPMI specification defines a system MSI service group which allows application processors to receive MSIs upon system events such as graceful shutdown/reboot request, CPU hotplug event, memory hotplug event, etc. Add an irqchip driver for the RISC-V RPMI system MSI service group to directly receive system MSIs in Linux kernel. Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-14-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
…nargs_prop mainline inclusion from mainline-6.17 commit e121be7 category: feature bugzilla: RVCK-Project#243 -------------------------------- Currently, acpi_fwnode_get_reference_args() delegates to the internal function __acpi_node_get_property_reference() to retrieve property references. However, this function does not handle the nargs_prop (cells property) parameter, and instead expects the number of arguments (nargs) to be known or hardcoded. As a result, when fwnode_property_get_reference_args() is used with a valid nargs_prop, the ACPI backend ignores it, whereas the Device Tree (DT) backend uses the #*-cells property from the reference node to determine the number of arguments dynamically. To support the nargs_prop in ACPI, refactor the code as follows: - Move the implementation from __acpi_node_get_property_reference() into acpi_fwnode_get_reference_args(). - Update __acpi_node_get_property_reference() to call the (now updated) acpi_fwnode_get_reference_args() passing NULL as nargs_prop to keep the behavior of __acpi_node_get_property_reference() intact. Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-15-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 159c86f category: feature bugzilla: RVCK-Project#243 -------------------------------- Currently, ACPI does not support the use of a nargs_prop (e.g., associated with a reference in fwnode_property_get_reference_args(). Instead, ACPI expects the number of arguments (nargs) to be explicitly passed or known. This behavior diverges from Open Firmware (OF), which allows the use of a #*-cells property in the referenced node to determine the number of arguments. Since fwnode_property_get_reference_args() is a common interface used across both OF and ACPI firmware paradigms, it is desirable to have a unified calling convention that works seamlessly for both. Add the support for ACPI to parse a nargs_prop from the referenced fwnode, aligning its behavior with the OF backend. This allows drivers and subsystems using fwnode_property_get_reference_args() to work in a firmware-agnostic way without having to hardcode or special-case argument counts for ACPI. Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-16-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 4215d1c category: feature bugzilla: RVCK-Project#243 -------------------------------- The RPMI System MSI interrupt controller (just like PLIC and APLIC) needs to probed prior to devices like GED which use interrupts provided by it. Also, it has dependency on the SBI MPXY mailbox device. Add HIDs of RPMI System MSI and SBI MPXY mailbox devices to the honor list so that those dependencies are handled. Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-17-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 694b2ef category: feature bugzilla: RVCK-Project#243 -------------------------------- Currently, the interrupt controller list is created without any order. Create the list sorted with the GSI base of the interrupt controllers. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-18-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 4d185fd category: feature bugzilla: RVCK-Project#243 -------------------------------- Some RISC-V interrupt controllers like RPMI based system MSI interrupt controllers do not have MADT entry defined. These interrupt controllers exist only in the namespace. ACPI spec defines _GSB method to get the GSI base of the interrupt controller, However, there is no such standard method to get the GSI range. To support such interrupt controllers, set the GSI range of such interrupt controllers to non-overlapping range and provide API for interrupt controller driver to update it with proper value. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-19-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit bb96fb5 category: feature bugzilla: RVCK-Project#243 -------------------------------- The RPMI System MSI device will provide GSIs to downstream devices (such as GED) so add it to the RISC-V GSI to fwnode mapping. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-20-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 3f5d7a5 category: feature bugzilla: RVCK-Project#243 -------------------------------- ACPI based loadable drivers which need MSIs will also need imsic_acpi_get_fwnode() to update the device MSI domain so export this function. Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-21-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 7e64042 category: feature bugzilla: RVCK-Project#243 -------------------------------- Add ACPI support for the RISC-V SBI message proxy (MPXY) based mailbox driver. Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-22-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 4752b0c category: feature bugzilla: RVCK-Project#243 -------------------------------- Add ACPI support for the RISC-V RPMI system MSI based irqchip driver. Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-23-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit f30d7cc category: feature bugzilla: RVCK-Project#243 -------------------------------- The GPIO keyboard and event device can be used to receive graceful shutdown or reboot input keys so let us enable it by default for RV64 (just like ARM64). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-24-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.17 commit 67b8766 category: feature bugzilla: RVCK-Project#243 -------------------------------- Add Rahul and myself as maintainers for RISC-V RPMI and MPXY drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-25-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
dist inclusion category: cleanup Link: RVCK-Project#252 -------------------------------- This reverts commit 9898f99. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
dist inclusion category: bugfix Link: RVCK-Project#258 -------------------------------- Commit 3d4a329 ("Revert chore: use xuantie instead of thead") removed the source line for drivers/clk/xuantie/Kconfig but did not add back the source line for drivers/clk/thead/Kconfig. This causes CONFIG_CLK_TH1520_FM to be unavailable in menuconfig, which leads to clock driver not being built and boot failures on TH1520 boards. Fixes: 3d4a329 ("Revert chore: use xuantie instead of thead") Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
dist inclusion category: bugfix Link: RVCK-Project#258 -------------------------------- The openEuler OpenSBI firmware looks for "xuantie,th1520-aon" compatible string and requires the "opensbi-mboxes" property to initialize the AON subsystem for CPU hotplug and suspend-to-RAM functionality. After the revert commit 3d4a329, the aon node only has "thead,th1520-aon" compatible which causes OpenSBI to fail with: "aon node not found in FDT" This patch fixes the aon node by: 1. Adding "xuantie,th1520-aon" compatible for OpenSBI compatibility 2. Adding "opensbi-mboxes" property pointing to mbox_910r 3. Adding third parameter to mboxes for proper mailbox channel config 4. Adding status = "okay" to enable the node Fixes: 3d4a329 ("Revert chore: use xuantie instead of thead") Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
dist inclusion category: cleanup Link: RVCK-Project#235 -------------------------------- This reverts commit 2e4869d. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
dist inclusion category: cleanup Link: RVCK-Project#235 -------------------------------- This reverts commit 61085f0. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
dist inclusion category: cleanup Link: RVCK-Project#235 -------------------------------- This reverts commit f57b43b. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from Linux 7.0-rc3 commit 30e7573 category: feature bugzilla: RVCK-Project#236 -------------------------------- Add a YAML schema for the T-HEAD TH1520 SoC reset controller. This controller manages resets for subsystems such as the GPU within the TH1520 SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Link: https://lore.kernel.org/r/20250303152511.494405-2-m.wilczynski@samsung.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from Linux 7.0-rc3 commit 4a65326 category: feature bugzilla: RVCK-Project#236 -------------------------------- Add reset controller driver for the T-HEAD TH1520 SoC that manages hardware reset lines for various subsystems. The driver currently implements support for GPU reset control, with infrastructure in place to extend support for NPU and Watchdog Timer resets in future updates. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Link: https://lore.kernel.org/r/20250303152511.494405-3-m.wilczynski@samsung.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from Linux 7.0-rc3 commit cf5e81d category: feature bugzilla: RVCK-Project#236 -------------------------------- Add the "gpu-clkgen" reset property to the AON device tree node. This allows the AON power domain driver to detect the capability to power sequence the GPU and spawn the necessary pwrseq-thead-gpu auxiliary driver for managing the GPU's complex power sequence. This commit also adds the prerequisite dt-bindings/reset/thead,th1520-reset.h include to make the TH1520_RESET_ID_GPU_CLKGEN available. This include was previously dropped during a conflict resolution [1]. Link: https://lore.kernel.org/all/aAvfn2mq0Ksi8DF2@x1/ [1] Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Drew Fustini <drew@pdp7.com> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Signed-off-by: Drew Fustini <drew@pdp7.com> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.7-rc8 commit 683c5bb category: feature bugzilla: RVCK-Project#256 -------------------------------- ENTRY()/END()/WEAK() macros are deprecated and we should make use of the new SYM_*() macros [1] for better annotation of symbols. Replace the deprecated ones with the new ones and fix wrong usage of END()/ENDPROC() to correctly describe the symbols. [1] https://docs.kernel.org/core-api/asm-annotations.html Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.7-rc8 commit e5ff012 category: feature bugzilla: RVCK-Project#256 -------------------------------- For the sake of coherency, use local labels in assembly when applicable. This also avoid kprobes being confused when applying a kprobe since the size of function is computed by checking where the next visible symbol is located. This might end up in computing some function size to be way shorter than expected and thus failing to apply kprobes to the specified offset. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.11 commit 1a74833 category: feature bugzilla: RVCK-Project#256 -------------------------------- Currently, userstacktrace is unsupported for riscv. So use the perf_callchain_user() code as blueprint to implement the arch_stack_walk_user() which add userstacktrace support on riscv. Meanwhile, we can use arch_stack_walk_user() to simplify the implementation of perf_callchain_user(). A ftrace test case is shown as below: # cd /sys/kernel/debug/tracing # echo 1 > options/userstacktrace # echo 1 > options/sym-userobj # echo 1 > events/sched/sched_process_fork/enable # cat trace ...... bash-178 [000] ...1. 97.968395: sched_process_fork: comm=bash pid=178 child_comm=bash child_pid=231 bash-178 [000] ...1. 97.970075: <user stack trace> => /lib/libc.so.6[+0xb5090] Also a simple perf test is ok as below: # perf record -e cpu-clock --call-graph fp top # perf report --call-graph ..... [[31m 66.54%[[m 0.00% top [kernel.kallsyms] [k] ret_from_exception | ---ret_from_exception | |--[[31m58.97%[[m--do_trap_ecall_u | | | |--[[31m17.34%[[m--__riscv_sys_read | | ksys_read | | | | | --[[31m16.88%[[m--vfs_read | | | | | |--[[31m10.90%[[m--seq_read Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Tested-by: Jinjie Ruan <ruanjinjie@huawei.com> Cc: Björn Töpel <bjorn@kernel.org> Link: https://lore.kernel.org/r/20240708032847.2998158-3-ruanjinjie@huawei.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit 5bb5ccb category: feature bugzilla: RVCK-Project#256 -------------------------------- Introduce basic guest support in perf, enabling it to distinguish between PMU interrupts in the host or guest, and collect fundamental information. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/a67d527dc1b11493fe11f7f53584772fdd983744.1728957131.git.zhouquan@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit eded675 category: feature bugzilla: RVCK-Project#256 -------------------------------- For the information collected on the host side, we need to identify which data originates from the guest and record these events separately, this can be achieved by having KVM register perf callbacks. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/00342d535311eb0629b9ba4f1e457a48e2abee33.1728957131.git.zhouquan@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
mainline inclusion from mainline-6.12-rc6 commit e403a90 category: feature bugzilla: RVCK-Project#256 -------------------------------- Order the object files alphabetically in the Makefile so that it is very predictable inserting new object files in the future. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20241020194734.58686-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>
riscv inclusion category: feature bugzilla: RVCK-Project#322 -------------------------------- Add the SpacemiT K3 USB3 combo PHY driver. On K3 the PCIe/USB subsystem provides three single-lane PIPE3 PHYs (PHY2/3/4) shared between PCIe Port C/D and USB3 Port B/C/D. Lane ownership is selected through the APMU PMUA_PCIE_SUBSYS_MGMT register: the driver acquires the syscon-apmu regmap, disables PCIe-A x8 mode and switches the requested lane to USB before bringing the PHY up, so USB3 operation is only possible when the conflicting PCIe x8 configuration is not in use. Bring-up performs R-calibration trim override (N/P trim) and PLL/PU lock polling via the HSIO APB spare registers, and exposes the standard generic-phy init/exit/power and set_speed operations for the xHCI/dwc3 stack. The driver also registers a Type-C orientation switch/mux so the combo PHY can follow cable orientation on Type-C ports. Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
riscv inclusion category: feature bugzilla: RVCK-Project#322 -------------------------------- Add the K3 USB3 controller and combo PHY nodes to k3.dtsi and enable them on the com260 board, wiring up the usb3_portb controller, its USB2/USB3 PHYs and the on-board VL817 hub. Signed-off-by: Yongchao Jia <yongchao.jia@spacemit.com>
USB: spacemit-k3: Add Spacemit K3 USB host controller support
dist inclusion category: cleanup Link: RVCK-Project#354 -------------------------------- This reverts commit 30843df. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
dist inclusion category: cleanup Link: RVCK-Project#354 -------------------------------- This reverts commit 4a43937. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
dist inclusion category: cleanup Link: RVCK-Project#354 -------------------------------- This reverts commit 3401b2a. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
…ector specification." dist inclusion category: cleanup Link: RVCK-Project#354 -------------------------------- This reverts commit d701970. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit c3f7c14 ("riscv: dts: allwinner: convert isa detection to new properties") category: feature Link: RVCK-Project#354 -------------------------------- Convert the D1 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231009-moonlight-gray-92debdc89f30@wendy Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit e576b7c ("dt-bindings: riscv: Add xtheadvector ISA extension description") category: feature Link: RVCK-Project#354 -------------------------------- The xtheadvector ISA extension is described on the T-Head extension spec Github page [1] at commit 95358cb2cca9. Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc [1] Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-1-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit bf6279b ("dt-bindings: cpus: add a thead vlen register length property") category: feature Link: RVCK-Project#354 -------------------------------- Add a property analogous to the vlenb CSR so that software can detect the vector length of each CPU prior to it being brought online. Currently software has to assume that the vector length read from the boot CPU applies to all possible CPUs. On T-Head CPUs implementing pre-ratification vector, reading the th.vlenb CSR may produce an illegal instruction trap, so this property is required on such systems. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-2-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit ce1daee ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree") category: feature Link: RVCK-Project#354 -------------------------------- The D1/D1s SoCs support xtheadvector so it can be included in the devicetree. Also include vlenb for the cpu. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-3-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit cddd638 ("riscv: Add thead and xtheadvector as a vendor extension") category: feature Link: RVCK-Project#354 -------------------------------- Add support to the kernel for THead vendor extensions with the target of the new extension xtheadvector. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit 377be47 ("riscv: vector: Use vlenb from DT for thead") category: feature Link: RVCK-Project#354 -------------------------------- If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-5-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit 66f1977 ("RISC-V: define the elements of the VCSR vector CSR") category: feature Link: RVCK-Project#354 -------------------------------- The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Acked-by: Guo Ren <guoren@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-6-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit b9a9314 ("riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT") category: feature Link: RVCK-Project#354 -------------------------------- The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT has an encoding of 0x9. Co-developed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-7-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> [zhenxing.zhu@linux.alibaba.com: adapted to rvck-6.6 baseline csr.h which already has partial CSR definitions] Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit 01e3313 ("riscv: Add xtheadvector instruction definitions") category: feature Link: RVCK-Project#354 -------------------------------- xtheadvector uses different encodings than standard vector for vsetvli and vector loads/stores. Write the instruction formats to be used in assembly code. Co-developed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-8-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit d863910 ("riscv: vector: Support xtheadvector save/restore") category: feature Link: RVCK-Project#354 -------------------------------- Use alternatives to add support for xtheadvector vector save/restore routines. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-9-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> [zhenxing.zhu@linux.alibaba.com: only vector.h hunks needed, other files already in rvck-6.6 baseline] Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
…ension mainline inclusion from mainline-6.14 commit 7fa00fd ("riscv: hwprobe: Document thead vendor extensions and xtheadvector extension") category: feature Link: RVCK-Project#354 -------------------------------- Document support for thead vendor extensions using the key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 and xtheadvector extension using the key RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Evan Green <evan@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-11-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit 57d7713 ("selftests: riscv: Fix vector tests") category: feature Link: RVCK-Project#354 -------------------------------- Overhaul the riscv vector tests to use kselftest_harness to help the test cases correctly report the results and decouple the individual test cases from each other. With this refactoring, only run the test cases if vector is reported and properly report the test case as skipped otherwise. The v_initval_nolibc test was previously not checking if vector was supported and used a function (malloc) which invalidates the state of the vector registers. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-12-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit c384c5d ("selftests: riscv: Support xtheadvector in vector tests") category: feature Link: RVCK-Project#354 -------------------------------- Extend existing vector tests to be compatible with the xtheadvector instructions. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-13-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.16 commit 4262bd0 ("riscv: vector: Fix context save/restore with xtheadvector") category: feature Link: RVCK-Project#354 -------------------------------- Previously only v0-v7 were correctly saved/restored, and the context of v8-v31 are damanged. Correctly save/restore v8-v31 to avoid breaking userspace. Fixes: d863910 ("riscv: vector: Support xtheadvector save/restore") Cc: stable@vger.kernel.org Signed-off-by: Han Gao <rabenda.cn@gmail.com> Tested-by: Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Yanteng Si <si.yanteng@linux.dev> Reviewed-by: Andy Chiu <andybnac@gmail.com> Link: https://lore.kernel.org/r/9b9eb2337f3d5336ce813721f8ebea51e0b2b553.1747994822.git.rabenda.cn@gmail.com Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
…ous_vlenb() mainline inclusion from mainline-6.18 commit 2dc99ea ("riscv: cpufeature: avoid uninitialized variable in has_thead_homogeneous_vlenb()") category: feature Link: RVCK-Project#354 -------------------------------- In has_thead_homogeneous_vlenb(), smatch detected that the vlenb variable could be used while uninitialized. It appears that this could happen if no CPUs described in DT have the "thead,vlenb" property. Fix by initializing vlenb to 0, which will keep thead_vlenb_of set to 0 (as it was statically initialized). This in turn will cause riscv_v_setup_vsize() to fall back to CSR probing - the desired result if thead,vlenb isn't provided in the DT data. While here, fix a nearby comment typo. Cc: stable@vger.kernel.org Cc: Charlie Jenkins <charlie@rivosinc.com> Fixes: 377be47 ("riscv: vector: Use vlenb from DT for thead") Signed-off-by: Paul Walmsley <pjw@kernel.org> Link: https://lore.kernel.org/r/22674afb-2fe8-2a83-1818-4c37bd554579@kernel.org Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.18 commit 9f393d8 ("riscv: dts: allwinner: d1: fix vlenb property") category: feature Link: RVCK-Project#354 -------------------------------- According to [1], the C906 vector registers are 128 bits wide. The 'thead,vlenb' property specifies the vector register length in bytes, so its value must be set to 16. [1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf Fixes: ce1daee ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree") Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.19 commit aef6dc0 ("riscv: dts: thead: add xtheadvector to the th1520 devicetree") category: feature Link: RVCK-Project#354 -------------------------------- The th1520 support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2]. This can be tested by passing the "mitigations=off" kernel parameter. Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1] Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Drew Fustini <fustini@kernel.org> [zhenxing.zhu@linux.alibaba.com: xtheadvector already in isa, only added thead,vlenb property] Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.11 commit ac295b6 ("riscv: vector: adjust minimum Vector requirement to ZVE32X") category: feature Link: RVCK-Project#354 -------------------------------- Make has_vector() to check for ZVE32X. Every in-kernel usage of V that requires a more complicate version of V must then call out explicitly. Also, change riscv_v_first_use_handler(), and boot code that calls riscv_v_setup_vsize() to accept ZVE32X. Most kernel/user interfaces requires minimum of ZVE32X. Thus, programs compiled and run with ZVE32X should be supported by the kernel on most aspects. This includes context-switch, signal, ptrace, prctl, and hwprobe. One exception is that ELF_HWCAP returns 'V' only if full V is supported on the platform. This means that the system without a full V must not rely on ELF_HWCAP to tell whether it is allowable to execute Vector without first invoking a prctl() check. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Acked-by: Joel Granados <j.granados@samsung.com> Link: https://lore.kernel.org/r/20240510-zve-detection-v5-7-0711bdd26c12@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> [zhenxing.zhu@linux.alibaba.com: partial backport, vector.h/cpufeature.c/vector.c already applied via baseline, only sys_hwprobe.c and uaccess.S hunks added] Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
|
开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/30614654906 参数解析结果
测试完成 详细结果:
Kunit Test Result[08:59:26] Testing complete. Ran 482 tests: passed: 465, skipped: 17
Kernel Build Result
Check Patch Result
LAVA Check (qemu)lava 执行失败. |
Author
|
主线回合代码 checkpatch 格式校验失败。 patch-20260731080725/0014-riscv-vector-Support-xtheadvector-save-restore.patch ERROR:SPACING: spaces required around that ':' (ctx:VxW)
|
Contributor
|
rvck-6.6已经rebase，请尽快rebase开发分支后push -f，该pr系th1520平台启动修复，会优先审阅合并。 |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
20 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
修复th1520 开启非对齐vector后启动崩溃。
将上游 xtheadvector 主线支持 backport 到 rvck-6.6。先 revert 基线 4 个旧改 commit,再合入 18 个上游 commit。共 22 commits。
Reverts (4)
Series 1: riscv: Add support for xtheadvector (v11, Charlie Jenkins)
Cover: https://lore.kernel.org/r/20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com
13 patches 合入 12 个,patch 10 (
21e49e64f307) 基线已有,跳过。e576b7cb8183dt-bindings: riscv: Add xtheadvector ISA extension descriptionbf6279b38a4bdt-bindings: cpus: add a thead vlen register length propertyce1daeeba600riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetreecddd63869f92riscv: Add thead and xtheadvector as a vendor extension377be47f90e4riscv: vector: Use vlenb from DT for thead66f197785d51RISC-V: define the elements of the VCSR vector CSRb9a931442451riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT (有差异,基线 csr.h 已有部分定义)01e3313e34d0riscv: Add xtheadvector instruction definitionsd863910eabafriscv: vector: Support xtheadvector save/restore (有差异,仅需 vector.h hunks)21e49e64f307riscv: hwprobe: Add thead vendor extension probing — 基线已有,跳过7fa00fd6ff53riscv: hwprobe: Document thead vendor extensions and xtheadvector extension57d7713af93eselftests: riscv: Fix vector testsc384c5d4a2aeselftests: riscv: Support xtheadvector in vector testsSeries 2: D1 dts isa-extensions 转换 (依赖补丁)
Link: https://lore.kernel.org/r/20231009-moonlight-gray-92debdc89f30@wendy
c3f7c14856ebriscv: dts: allwinner: convert isa detection to new propertiesSeries 3: zve-detection v5 (仅 patch 7)
Link: https://lore.kernel.org/r/20240510-zve-detection-v5-7-0711bdd26c12@sifive.com
ac295b67422driscv: vector: adjust minimum Vector requirement to ZVE32X (有差异,部分 backport,仅 sys_hwprobe.c + uaccess.S)fixes (4)
4262bd0d9cc7riscv: vector: Fix context save/restore with xtheadvectorhttps://lore.kernel.org/r/9b9eb2337f3d5336ce813721f8ebea51e0b2b553.1747994822.git.rabenda.cn@gmail.com
2dc99ea27276riscv: cpufeature: avoid uninitialized variable in has_thead_homogeneous_vlenb()https://lore.kernel.org/r/22674afb-2fe8-2a83-1818-4c37bd554579@kernel.org
9f393d8e757friscv: dts: allwinner: d1: fix vlenb propertyhttps://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com
aef6dc006696riscv: dts: thead: add xtheadvector to the th1520 devicetree (有差异,仅添加 thead,vlenb 属性)https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/
测试
fixed: #354