RISC-V: KVM: Align kvm_vcpu_state to cacheline boundary - #361
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The kvm_vcpu_state structure is accessed frequently during VM entry/exit. Misalignment can cause a single structure to span multiple cache lines, leading to increased cache misses and performance degradation. Align the structure to the maximum cache line size to ensure it resides within a single cache line, reducing cache contention and improving overall KVM performance. Signed-off-by: BillXiang <xiangwencheng@lanxincomputing.com>
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/31171223549 参数解析结果
测试完成 详细结果:
Kunit Test Result[10:48:09] Testing complete. Ran 482 tests: passed: 465, skipped: 17
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riscv inclusion
category: kvm
bugzilla: #360
The kvm_vcpu_state structure is accessed frequently during VM entry/exit. Misalignment can cause a single structure to span multiple cache lines, leading to increased cache misses and performance degradation.
Align the structure to the maximum cache line size to ensure it resides within a single cache line, reducing cache contention and improving overall KVM performance.