Add ihp-sg13cmos5l#3988
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sorry, I already fixed my branch but wanted to wait for the CI results.
I moved this change into a dedicated commit. This file is actually not used and sg13g2_io.cdl is used.
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@maliberty one nandgate45 test failed. Can you restart this test? Can you please also enable the ihp-sg13cmos5l runs after this PR got merged? |
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Also fixed |
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Probably the failure just needs a merge of master to resolve as pr-merge is already passing. |
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Are the standard cells the same (ie could we just link the lef & lib & cdl)? |
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no, but the sram macros are the same and I replaced them with links to the same files in the ihp-sg13g2. Ideally we can move all SRAM macros into a common |
That did work, thanks! |
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does this process not need tapcells?
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No, they don't have one. Same for the SG13G2 process.
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| # IHP SG13CMOS5L official port for OpenROAD-flow-scripts | |||
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How about a link to the upstream at least?
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Do you mind if I update the README for both IHP processes afterwards? SG13G2 is also TBD...
I think there are a couple more places where ORFS could mention support for IHP.
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That's fine so long as you'll follow up on it.
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It's on my list together with the DRT-0349 warning. Currently working on tape-outs, but I have more time in April.
Add IHP's SG13CMOS5L PDK. This technology is almost identical to SG13G2, but is missing the HBTs and has only 5 metal layers. It's missing Metal5 and TopMetal2 for cheaper and faster production runs. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
sg13g2_iocell.cdl is not used anymore and sg13g2_io.cdl is used instead. Remove this old .cdl file. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add all ihp-sg13g2 examples for the CMOS5L PDK and modify all required parts. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
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@maliberty updated tech lef file with X and Y pitch. |
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This technology is almost identical to SG13G2, but is missing
the HBTs and has only 5 metal layers.
It's missing Metal5 and TopMetal2 for cheaper and faster
production runs.