riscv64: do not trap on division by zero (RISC-V defines it)

[DORA-B]

Target: https://github.com/angr/vex — priv/guest_riscv64_toIR.c
Kind: PR (patch + repro). Stacked on PR #83 (remainder fixes) — the two
touch the same eight div/rem cases; #83 should merge first, after which this
PR's diff reduces to the divide-by-zero delta.
Verified: angr/pyvex 9.2.221 / 9.3.0 and current master.

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Summary

RISC-V's M extension defines integer divide-by-zero and the single signed
overflow case as non-trapping, with fixed results:

op	divisor 0	INT_MIN ÷ −1
div	−1 (all ones)	INT_MIN
divu	2^XLEN−1 (all ones)	—
rem	dividend	0
remu	dividend	—

(The spec: "We considered raising exceptions on integer divide by zero…
Instead… no exceptions are raised.")

But pyvex's generic lifting/zerodivision.py (ZeroDivisionPostProcessor)
inserts an Ijk_SigFPE_IntDiv exit before every Div/Mod op — correct
for x86/ARM where ÷0 traps, wrong for RISC-V. Result: a RISC-V program doing
divu x, x, 0 takes a spurious SIGFPE and never gets the defined all-ones
value (under angr this surfaces as a divide by zero! exception).

Reproduction (before the fix)

import angr, claripy, archinfo, logging
[logging.getLogger(n).setLevel(logging.CRITICAL) for n in ('angr','pyvex','cle')]
A = archinfo.ArchRISCV64()
def run(word, a, b):
    st = angr.load_shellcode(word.to_bytes(4,'little'), arch=A).factory.blank_state(addr=0)
    st.regs.x6 = claripy.BVV(a,64); st.regs.x7 = claripy.BVV(b,64)
    try:    return hex(st.solver.eval(st.step(num_inst=1).successors[0].regs.x5))
    except Exception as e: return 'EXC: ' + str(e)
print(run(0x027352b3, 5, 0))   # divu x5,x6,x7 ; b=0 -> 'EXC: divide by zero!'  (spec: all ones)
print(run(0x027362b3, 5, 0))   # rem  x5,x6,x7 ; b=0 -> 'EXC: divide by zero!'  (spec: 5)