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Issues
- chipsalliance/rocket-chip#3847 · opened
on Nov 9, 2026 - chipsalliance/rocket-chip#3846 · opened
on Nov 9, 2026 - chipsalliance/rocket-chip#3845 · opened
on Nov 9, 2026 - chipsalliance/rocket-chip#3844 · opened
on Nov 9, 2026 - chipsalliance/rocket-chip#3843 · opened
on Nov 9, 2026 - chipsalliance/rocket-chip#3842 · opened
on Nov 9, 2026 - chipsalliance/rocket-chip#3841 · opened
on Nov 3, 2026 - chipsalliance/rocket-chip#3840 · opened
on Oct 19, 2026 - chipsalliance/rocket-chip#3838 · opened
on Oct 11, 2026 - chipsalliance/rocket-chip#3836 · opened
on Oct 5, 2026 - chipsalliance/rocket-chip#3834 · opened
on Sep 23, 2026 - chipsalliance/rocket-chip#3833 · opened
on Sep 23, 2026 - chipsalliance/rocket-chip#3832 · opened
on Sep 23, 2026 - chipsalliance/rocket-chip#3831 · opened
on Sep 20, 2026 - chipsalliance/rocket-chip#3829 · opened
on Sep 19, 2026 - chipsalliance/rocket-chip#3828 · opened
on Sep 19, 2026 mie is read back unmasked from an un-reset register, so its non-writable bits are not read-only zero
chipsalliance/rocket-chip#3827 · openedon Sep 12, 2026 mstatus.TW is gated on usingSupervisor instead of usingUser: an M+U hart cannot trap WFI from U-mode
chipsalliance/rocket-chip#3826 · openedon Sep 12, 2026 - chipsalliance/rocket-chip#3819 · opened
on Jul 15, 2026 - chipsalliance/rocket-chip#3817 · opened
on Jul 8, 2026 - chipsalliance/rocket-chip#3816 · opened
on Jul 4, 2026 - chipsalliance/rocket-chip#3815 · opened
on Jul 4, 2026 - chipsalliance/rocket-chip#3814 · opened
on Jul 4, 2026 - chipsalliance/rocket-chip#3812 · opened
on Jun 26, 2026 - chipsalliance/rocket-chip#3811 · opened
on Jun 26, 2026