RiscV_tapeout_2025_RTL_week1

Week 1 of the vsd 2025 tapeout program, i.e, RTL design and synthesis using sky130

Table of Contents

• Week 1 Structure
• License
• Acknowledgements

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Week 1 structure

• Verilog RTL design and simulation

• Using Icarus Verilog and GTKWave for simulation and waveform analysis

• Logic synthesis using Yosys and the SKY130 open-source PDK

• Key digital design concepts: testbenches, timing libraries, D flip-flop coding styles, and optimization techniques

• Day 1: Introduction to Verilog RTL Design & Synthesis

• Day 2: Timing Libraries, Synthesis Approaches, and Efficient Flip-Flop Coding

• Day 3: Combinational and Sequential Optimization

• Day 4: Gate-Level Simulation (GLS), Blocking vs. Non-Blocking in Verilog, and Synthesis-Simulation Mismatch

• Day 5: Optimization in Synthesis

• ISSUES

Each day’s README includes:

• Clear explanations of the day’s concepts
• Step-by-step practical labs with code and screenshots
• Tips and best practices for RTL design

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License

This project is licensed under the Attribution 4.0 International License - see the LICENSE file for details.

Acknowledgements 👑

• Kunal Ghosh
• Open-source tools providers like Yosys and Sky130 PDK.