Add per-hart interrupts for RISCV#763
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Add per-hart interrupts (riscv,timer and riscv,cpu-intc) for RISCV Signed-off-by: Dhriti Sree Rompicharla <DhritiSree.Rompicharla@amd.com>
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@onkarharsh @sivadur Please review this change |
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Looks good to me |
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Add per-hart interrupts (riscv,timer and riscv,cpu-intc) for RISCV