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…ot see it 310: `gen-verilog` mapped `>>` to Verilog's logical `>>` on signed operands, and the decisive evidence was not in the compiler. All 559 generated modules held two `>>>`, both inside string literals -- and those literals are this project's own hand-written golden CORDIC RTL, which writes `y0 >>> 1` for the identical rotation. The project knew the right operator and the backend emitted it zero times. A hand-written reference in the repository is an oracle the generator can be measured against, and it costs one grep. 311: four defects fixed this pass and not one moved an acceptance number -- the step becoming the loop body, the dropped width suffix, the logical shift, the truncated test that reported OK. Every one produced output the target compiler was happy with, so a gate asking "does it compile" cannot see the whole interesting class. What saw them: a second backend to disagree with, a hand-written artefact to compare against, and simulating the emitted module instead of reading it. Refs #2868
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Two sections from #2868.
310 — the repository already wrote the correct form, by hand, next door.
gen-verilogmapped>>to Verilog's logical>>on signed operands; simulated on the actual generated module,cordic_x_next(100, −64, shift=2)returned −16268 where the spec, C and Zig all say 116.The decisive evidence was in the corpus, not the compiler: all 559 generated modules held two
>>>, and both were inside string literals — this project's own hand-written golden CORDIC RTL, which writesy0 >>> 1for the identical rotation. The project knew the right operator and the backend emitted it zero times. A hand-written reference in the repository is an oracle, and it costs one grep.311 — acceptance could not have caught any of it. Four defects fixed in one pass; not one moved an acceptance number:
while (c) : (step)1u64 << nshifted at u32 and panicked>>on signedEvery one produced output the target compiler was happy with. A gate asking does it compile cannot see any defect whose whole nature is that it compiles. What saw them: a second backend to disagree with, a hand-written artefact to compare against, and simulating the emitted module instead of reading it.
Refs #2868