[libclc] Define 64-bit atomic compare_exchange for NVPTX#22750
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The compare_exchange definition guard grouped __NVPTX__ with __SPIR32__ and only emitted atomics for 32-bit types, so 64-bit integer __clc_atomic_compare_exchange was declared (via atomic_decl.inc) but never defined for CUDA, causing "Unresolved extern function '_Z29__clc_atomic_compare_exchange...'" (ptxas fatal) for 64-bit CAS. Match the guard used by the sibling clc_atomic_def.inc (restrict only __SPIR32__ to 32-bit) so both CUDA (NVPTX) and HIP (AMDGPU) get 64-bit compare_exchange definitions. Co-authored-by: Cursor <cursoragent@cursor.com>
bratpiorka
approved these changes
Jul 24, 2026
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Summary
The
compare_exchangedefinition guard inclc_atomic_compare_exchange.incgrouped__NVPTX__together with__SPIR32__and only emitted atomics for 32-bit types. As a result, the 64-bit integer__clc_atomic_compare_exchangewas declared (viaatomic_decl.inc) but never defined for CUDA, producingUnresolved extern function '_Z29__clc_atomic_compare_exchange...'(ptxas fatal) whenever a 64-bit compare-and-swap was used on NVPTX.This changes the guard to match the sibling
clc_atomic_def.inc(restrict only__SPIR32__to 32-bit), so both CUDA (NVPTX) and HIP (AMDGPU) get 64-bitcompare_exchangedefinitions.Test plan
libspirv.bc/libclc.bcand confirmed the 64-bit__spirv_AtomicCompareExchangeforint64(...liiill) anduint64(...miiimm) are now defined in both global (AS1) and local (AS3) address spaces (previously unresolved).local-ht-syclbenchmark (HeCBench) with-fsycl-targets=nvptx64-nvidia-cuda --cuda-gpu-arch=sm_80on an NVIDIA A100 (CUDA 12.8): all four Kmer sizes (21, 33, 55, 77) PASSED.