Merge pull request #24 from Minchan-Kwon/master

[Docs] Added Image Description of Benchmark Suite

Author: AlexandreSinger

auto_generated/README.md

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+# Auto Generated Suite
+
+This is a benchmark suite automatically generated to test a CAD tool's ability to parse Synopsys Design Constraints.
+It is a collection of all valid combinations of SDCs and their corresponding RTL files written in Verilog. 
+The specific commands included in this benchmark are listed in the [syntax document](../docs/syntax/README.md).
+
+![Syntax-Suite.png](./images/Syntax-Suite.png)
+
+All of the SDCs in this suite have been generated using generate_sdc.py included in the repository. 
+This Python script will exhaustively generate SDCs that fit the syntax description. 
+We then pass the SDCs through OpenSTA to filter out any invalid SDCs that may have been generated. 
+This suite is made up of the valid SDCs and the RTL files that go along with them in the CAD flow.  
+

auto_generated/images/Syntax-Suite.png

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+/*
+Command: get_clocks
+Description:
+    -Returns a list of clocks matching patterns
+    
+SDC Example:
+    get_clocks clk1
+    get_clocks -quiet clk1098
+*/
+
+//Main module
+module get_clocks(
+    input wire clk1, 
+    input wire clk2,
+    input wire clk_gen,
+    input wire clock,
+    output reg dummy_out
+);
+    initial dummy_out = 1'b1;
+
+    always @(posedge clk1 or posedge clk2 or posedge clk_gen or posedge clock) begin
+        dummy_out <= ~dummy_out;
+    end
+
+endmodule
+

auto_generated/images/Timing-Suite.png

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+/*
+Command: get_pins
+Description:
+    -Returns a list of all instance pins matching patterns
+    
+SDC Example:
+    get_pins -regexp u1/D
+    get_pins u1/D
+*/
+
+//Main module
+module get_pins(
+    input wire clk, 
+    input wire data_in,
+    output reg [1:0] data_out
+);
+    wire u1_out, u2_out;
+
+    //Datapath
+    DFF u1(.clk(clk), .D(data_in), .Q(u1_out));
+    DFF u2(.clk(clk), .D(~data_in), .Q(u2_out));
+
+    assign data_out = {u1_out, u2_out};
+
+endmodule
+
+module DFF(
+    input wire clk,
+    input wire D,
+    output reg Q
+);
+    always @(posedge clk) begin
+        Q <= D;
+    end
+endmodule

auto_generated/netlist_files/get_clocks_netlist.v

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+/*
+Command: get_ports
+Description:
+    -Returns a list of all top level ports that match patterns 
+    
+SDC Example:
+    get_ports data*
+    get_ports -regexp rst
+*/
+
+module get_ports(
+    input wire clk,
+    input wire rst,
+    input wire data1_in,
+    input wire data2_in,
+    input wire valid_in,
+    output reg result_out,
+    output wire ready_out
+);
+    //ready_out is always 1 for this simple module
+    assign ready_out = 1'b1;
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            result_out <= 1'b0;
+        end
+        else if (valid_in) begin
+            result_out <= data1_in + data2_in;
+        end
+    end
+
+endmodule

auto_generated/netlist_files/get_pins_netlist.v

@@ -1,5 +1,7 @@
 # SDC Syntax
 
+![SDC_Syntax.png](./docs/images/Synopsys-Design-Constraints.png)
+
 ## Timing Constraints
 
 ### create_clock