Skip to content

feat(riscv64): support Asterinas OS as guest on hvisor#325

Open
YZYY95K wants to merge 3 commits into
syswonder:devfrom
YZYY95K:feature/asterinas-support
Open

feat(riscv64): support Asterinas OS as guest on hvisor#325
YZYY95K wants to merge 3 commits into
syswonder:devfrom
YZYY95K:feature/asterinas-support

Conversation

@YZYY95K

@YZYY95K YZYY95K commented Jun 28, 2026

Copy link
Copy Markdown

概述

在 hvisor 虚拟化平台上支持 Asterinas(星绽)操作系统作为 Guest OS 运行。本 PR 为 CCF 开源创新大赛赛题「在hvisor虚拟化平台上支持Asterinas(星绽)操作系统」提交。

主要改动

1. 修复 HENVCFG ADUE 位配置 (src/arch/riscv64/cpu.rs)

  • 修正 ADUE 位为 bit 61(原代码缺失),启用 SVADU 扩展
  • 添加 HSTATUS_SPVTW 位,trap guest satp 写入
  • 启用 STCE 扩展(bit 63)支持 Sstc

2. 新增 SBI DBCN 和 SRST 扩展处理 (src/arch/riscv64/sbi.rs)

  • DBCN (0x4442434E): 控制台输出,直接写 UART 硬件避免递归 trap
  • SRST (0x53525354): 系统重置,支持 guest 优雅关机
  • 降低调试日志级别(info! → trace!/debug!)

3. 增强 Guest 异常处理 (src/arch/riscv64/trap.rs)

  • 处理 Guest 未设置 trap vector (vtvec=0) 时的指令页错误
  • 自动禁用 VSTIMECMP 并清除挂起中断,避免死循环
  • 降低 IRQ 调试日志级别

4. Asterinas 平台配置 (platform/riscv64/qemu-plic/)

  • board.rs: 配置 Asterinas 内存布局(16MB kernel + 144MB RAM)
  • platform.mk: 更新 kernel/DTB 路径,添加 initramfs 加载
  • image/dts/zone0-asterinas.dts: Asterinas 专用设备树,含 initramfs 参数

5. 技术文档

  • docs/asterinas-support.md: 详细技术说明(设计思路、实现方案、测试验证、创新点)
  • docs/README-asterinas.md: 快速开始指南和目录结构

测试验证

在 QEMU virt (4 CPU, 4GB RAM) 验证 Asterinas 成功启动:

[INFO 0] hvisor: hvisor started...
[INFO 0] hvisor::arch::riscv64::sbi: SBI SRST: system_reset type=0, reason=0
Hello from Asterinas on hvisor!
Init running, mounting proc and sys...
Init done. Powering off.

技术要点

  1. SVADU 扩展: 通过 HENVCFG.ADUE (bit 61) 启用硬件自动 A/D 位更新
  2. SBI 适配: 实现 DBCN/SRST 扩展,兼容 Asterinas 的 SBI 调用
  3. 内存映射: Stage-2 页表映射 guest IPA (0x80200000) 到 host PA (0x90000000)
  4. Initramfs: 提供 minimal init 程序和 CPIO 文件系统

相关 Issue

GitLink Issue: https://www.gitlink.org.cn/syswonder/hvisor/issues/145159

比赛

CCF 开源创新大赛 - 在hvisor虚拟化平台上支持Asterinas操作系统

agicy and others added 3 commits April 26, 2026 21:34
Release v0.5: Merge dev into main
Add support for running Asterinas (a Rust-based OS kernel) as a guest
OS on the hvisor hypervisor for RISC-V64. Verified on QEMU virt with
4 CPUs and 4GB RAM.

Key changes:

1. Fix HENVCFG ADUE bit position (cpu.rs):
   - Set ADUE at bit 61 (was missing entirely) to enable SVADU
     (automatic A/D bit updates for guest page tables).
   - Without this, guest page table walks trigger page faults because
     the hardware cannot update A/D bits, causing boot failure.
   - Also set HSTATUS_SPVTW (bit 56) to trap guest satp writes.

2. Add SBI DBCN and SRST extension handlers (sbi.rs):
   - DBCN (Debug Console): Asterinas uses sbi_rt::console_write_byte
     for early console output. Handler writes directly to UART
     (0x10000000) to avoid recursive ecall traps in HS-mode.
   - SRST (System Reset): Asterinas uses sbi_rt::system_reset for
     clean shutdown/reboot.

3. Add guest VS-stage page fault handler (trap.rs):
   - Handle instruction guest-page fault (cause 20) with recovery
     logic for premature timer interrupts (vtvec=0 case).
   - Add guest_vs_page_fault_handler to manually set A/D bits as a
     fallback when SVADU is not effective.
   - Guard timer interrupt injection against unset vtvec.

4. Configure Asterinas memory layout (board.rs):
   - Stage-2 maps guest IPA 0x80200000 to host PA 0x90000000
     (Asterinas is linked at 0x80200000).
   - Map RAM, DTB, UART, virtio-mmio, and PLIC regions.

5. Add Asterinas device tree (zone0-asterinas.dts):
   - Includes initrd-start/initrd-end for initramfs loading.
   - Configures UART, virtio-mmio console, and PLIC.

6. Add boot scripts and utilities:
   - boot_asterinas.sh: QEMU launch script for testing.
   - extract_output.py: Parse Asterinas console output from hvisor logs.
Add comprehensive technical documentation for Asterinas-on-hvisor support:
- docs/asterinas-support.md: Technical specification covering design,
  implementation, testing, and innovation points
- docs/README-asterinas.md: Quick start guide and directory structure

These documents fulfill the competition requirement for a technical
description document and README for the Asterinas adaptation work.
@github-actions github-actions Bot added riscv64 feature New feature or request labels Jun 28, 2026
@Solicey

Solicey commented Jun 30, 2026

Copy link
Copy Markdown
Contributor

It is not necessary to add documentation to this repo, please remove markdown files under doc. You can submit your documents in the comment section of this PR.

Comment thread src/arch/riscv64/entry.rs
Comment on lines -1 to -15
// Copyright (c) 2025 Syswonder
// hvisor is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
// FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
//
// Syswonder Website:
// https://www.syswonder.org
//
// Authors:
// Jingyu Liu <liujingyu24s@ict.ac.cn>

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It looks like you've introduced some whitespace or line-ending changes that are causing the entire file to show as a diff, even without actual logic modifications.

@Solicey

Solicey commented Jun 30, 2026

Copy link
Copy Markdown
Contributor

Please include a detailed "quick start" guide in your comments so we can easily reproduce your work. You can follow the style of this example: https://hvisor.syswonder.org/chap02/QemuRISC-V.html

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

feature New feature or request riscv64

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants