Test-bench Architecture:
How to run project:
- Create project on questasim, in the same folder.
- Run 'do run/run_uvm.do' from simulator terminal for uvm environment test, or 'do run/run.do' for direct testbench.
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tonyalfred/Synchronous-FIFO-Design-and-Verification-using-Verilog-and-UVM
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Build a UVM Environment for an a Synchronous FIFO. Concepts like virtual sequencer, reset agents, assertions were used.
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