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@wsnyder FYI this works, but I will only land it after verilator/verilator#6746

@gezalore gezalore marked this pull request as ready for review December 8, 2025 22:11
@gezalore gezalore merged commit c2a79fe into verilator:main Dec 8, 2025
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@gezalore gezalore deleted the import-caliptra branch December 8, 2025 22:12
@solomatnikov
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https://github.com/chipsalliance/caliptra-ss is another interesting design

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gezalore commented Dec 11, 2025

Thanks @solomatnikov! Is there an explainer on what's the difference from caliptra-rtl? (beyond the one-liner at the top of the readme)

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solomatnikov commented Dec 11, 2025

https://github.com/chipsalliance/caliptra-ss is larger IP that includes https://github.com/chipsalliance/caliptra-rtl, 2nd RISC-V core, https://github.com/chipsalliance/i3c-core, boot, life-cycle, etc.

https://github.com/chipsalliance/caliptra-ss/blob/main/docs/images/CaliptraSubsystem.png

It is an SRoT + MCU designed by MS to be open source and auditable for security and to be integrated into datacenter chips.

https://github.com/chipsalliance/caliptra-mcu-sw runs verilator sims AFAIK.

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