Skip to content
View vohoangnguyennnn's full-sized avatar
6 followers · 26 following

Achievements

Achievement: YOLOAchievement: Pull Shark

Achievements

Achievement: YOLOAchievement: Pull Shark

Highlights

  • Pro

Block or report vohoangnguyennnn

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
vohoangnguyennnn/README.md
Vo Hoang Nguyen - Verilog | SystemVerilog | RISC-V
Typing SVG

Hi 👋, I'm Vo Hoang Nguyen

A Passionate Hardware & IC Design Engineer-in-training

Third-year student majoring in Electronics and Communications Engineering, focused on IC Design, CPU/SoC architecture, and AI-related hardware systems. I love digging into how silicon actually makes computers think — let's connect and build something together!

Profile views

👤 About Me

  • 🌱 Currently studying IC Design
  • 🚀 Diving deeper into CPU/SoC architecture and digital front-end design flows
  • 💡 Passionate about hardware design, CPU/SoC architecture, and AI-related hardware systems
  • 💬 Ask me about Digital Logic Design | Verilog/SystemVerilog | CPU Architecture
  • 🤝 Looking to collaborate on RISC-V / CPU / SoC front-end design projects
  • 📫 How to reach me: connect via the links below
 Circuit board animation

🛠️ Skills & Tools

Verilog SystemVerilog RISC--V C Python Linux Git

🌍 Connect with Me

LinkedIn Facebook

Pinned Loading

  1. riscv-rv32im-core riscv-rv32im-core Public

    5-stage RV32IM RISC-V CPU and FPGA SoC in SystemVerilog, featuring forwarding, hazard control, machine-mode CSR/traps, precise timer interrupts, TCM, UART, GPIO, and FreeRTOS bring-up.

    SystemVerilog 6 1

  2. smart-parking-fpga-AI smart-parking-fpga-AI Public

    RTL-based smart parking controller with UART protocol, FPGA verification, ESP32 gateway and AI license plate recognition integration

    SystemVerilog 6 1

  3. Asynchronous-FIFO Asynchronous-FIFO Public

    Asynchronous FIFO design in SystemVerilog and testbench

    SystemVerilog

  4. verilog-digital-design verilog-digital-design Public

    Verilog implementations of fundamental digital circuits with testbench and simulation support.

    Verilog 1