XgenSilicon

Reducing power, cost, and development time for edge LLM deployment.

Our mission is to make custom AI hardware accessible, efficient, and scalable for edge applications. We automate the complete ASIC pipeline — from model in to GDSII out — combining a hardware-aware ML compiler, reinforcement-learning-driven design exploration, and a library of scalable RISC-V accelerator building blocks to optimize power, performance, and area for on-device inference.