flow: move eliminate_dead_logic into synth_odb.tcl#4190
flow: move eliminate_dead_logic into synth_odb.tcl#4190oharboe wants to merge 2 commits intoThe-OpenROAD-Project:masterfrom
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eliminate_dead_logic is a pure netlist transform: it does not need a die area, bterm placement or routing layers. Running it in synth_odb.tcl means 1_synth.odb already reflects the live design instead of dropping its instance count between synth and floorplan. This matters for parallel synthesis flows (e.g., MegaBoom) where yosys only sees a slice of the design at a time and cannot prune logic that is dead only when looking at the whole design. In those flows this step has historically eliminated ~50% of the design. Add a docstring above the remaining synthesis-looking transforms in floorplan.tcl (repair_tie_fanout, replace_arith_modules, remove_buffers, repair_timing_helper) explaining why they cannot follow: initialize_floorplan and set_routing_layers above set up the bterm boundary placement and the routing layer stack that timing-aware optimization relies on for parasitic estimation. Moving these calls into synth_odb.tcl was tried in PR The-OpenROAD-Project#4187 and regressed setup TNS by 1.7-46x on I/O-heavy designs (asap7/aes-block 2.5x, asap7/jpeg_lvt 37x, asap7/swerv_wrapper 46x finish-hold-TNS, nangate45/ariane133 1.7x); internal-logic-dominated designs like asap7/ibex were unaffected once the tie-fanout ordering was preserved, but the I/O-heavy regressions made the broader move untenable. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Code Review
This pull request moves the eliminate_dead_logic command from the floorplan stage to the synthesis stage to optimize parallel synthesis flows and adds documentation explaining the move. The feedback suggests wrapping the command in log_cmd to ensure its execution and duration are properly logged, maintaining consistency with other major flow commands.
| # stay in floorplan.tcl — moving them here was tried in PR #4187 and | ||
| # regressed setup TNS by 1.7-46x on I/O-heavy designs (asap7/aes-block, | ||
| # asap7/jpeg_lvt, asap7/swerv_wrapper, nangate45/ariane133). | ||
| eliminate_dead_logic |
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Since eliminate_dead_logic is a significant netlist transformation that can be time-consuming (as noted in the comments, it can prune up to 50% of some designs), it should be wrapped in log_cmd. This ensures that its execution is recorded in the logs along with its duration, maintaining consistency with how other major tool commands (like link_design, read_db, etc.) are handled in the flow.
log_cmd eliminate_dead_logic
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I think the above conclusions are just a symptom of the issue codex pointed out in your other PR |
eliminate_dead_logic can prune up to ~50% of a parallel-synth design (e.g., MegaBoom). log_cmd echoes the command line and reports duration when it exceeds 5 s, matching how other potentially expensive flow commands (link_design, read_db, repair_timing, write_db, etc.) are logged. Reported by gemini-code-assist on PR The-OpenROAD-Project#4190. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
I backed down from moving more stuff into synth_odb.tcl. The main confusion came from a massive drop in instances from synth to floorplan, fixed here. |
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@maliberty A much less ambitious PR that minimizes surprises. There's synthesis like work done in floorplan.tcl, like swap arith operators, leave that be for now. |
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Summary
eliminate_dead_logicfromfloorplan.tclintosynth_odb.tclso1_synth.odbreflects the live design.floorplan.tcl(repair_tie_fanout,replace_arith_modules,remove_buffers,repair_timing_helper) explaining why they cannot follow: synthesis is not I/O-pin-aware, and these calls depend oninitialize_floorplanhaving placed bterms on the die boundary andset_routing_layershaving set up the layer stack used for parasitic estimation.Why only
eliminate_dead_logiceliminate_dead_logicis a pure netlist transform — it does not read pin locations or routing layers, so the move is safe. It also matters for parallel synthesis flows (e.g., MegaBoom) where yosys only sees a slice of the design and cannot prune logic that is dead only when viewed whole; in those flows this step has historically pruned ~50% of the design.Why the other four stay in
floorplan.tclThis was attempted in #4187 (closed). Empirical result vs. master/1387 (deterministic baseline across multiple master CI runs):
I/O-heavy designs regress materially when timing-aware transforms run before bterm placement and routing-layer setup; internal-logic-dominated designs are unaffected. Splitting
eliminate_dead_logic(which is pure netlist) from the rest of the block (which is timing-aware) keeps the only safe move from #4187 and documents the constraint inline so the next attempt avoids the same pitfall.Test plan
1_synth.odbinstance count for asap7/ibex drops to its post-pruning value (no surprise instance-count drop between synth and floorplan).🤖 Generated with Claude Code