flow: move eliminate_dead_logic into synth_odb.tcl

flow/scripts/floorplan.tcl

@@ -32,10 +32,6 @@ proc report_unused_masters { } {
 
 report_unused_masters
 
-# Eliminate dead logic
-eliminate_dead_logic
-
-
 #Run check_setup
 puts "\n=========================================================================="
 puts "Floorplan check_setup"
@@ -116,6 +112,22 @@ if { [env_var_exists_and_non_empty FASTROUTE_TCL] } {
 
 source_env_var_if_exists FOOTPRINT_TCL
 
+# The transforms below (repair_tie_fanout, replace_arith_modules,
+# remove_buffers, repair_timing_helper) look like synthesis-stage
+# operations: they all act on the netlist and don't touch placement.
+# But they DO depend on having a floorplan in place — initialize_floorplan
+# above placed the bterms on the die boundary and set_routing_layers
+# configured the layer stack used for parasitic estimation. Without that
+# context, top-level ports look like they're at (0,0) and timing analysis
+# misjudges paths into/out of I/O.
+#
+# PR #4187 tried moving this block to synth_odb.tcl. It regressed setup
+# TNS by 1.7-46x on I/O-heavy designs (asap7/aes-block 2.5x, asap7/jpeg_lvt
+# 37x, asap7/swerv_wrapper 46x finish-hold-TNS, nangate45/ariane133 1.7x)
+# while leaving internal-logic-dominated designs like asap7/ibex
+# unchanged. The move was reverted; only eliminate_dead_logic stayed in
+# synth_odb.tcl because it is a pure netlist transform that doesn't
+# depend on placement or routing-layer context.
 if { !$::env(SKIP_REPAIR_TIE_FANOUT) } {
   # This needs to come before any call to remove_buffers.  You could have one
   # tie driving multiple buffers that drive multiple outputs.

flow/scripts/synth_odb.tcl

@@ -4,6 +4,26 @@ erase_non_stage_variables synth
 load_design 1_2_yosys.v 1_2_yosys.sdc
 source_step_tcl PRE SYNTH
 
+# Eliminate dead logic before writing the synthesis odb so that
+# 1_synth.odb already reflects the live design.
+#
+# This matters for parallel synthesis flows (e.g., MegaBoom) where yosys
+# only sees a slice of the design at a time and cannot prune logic that
+# is dead only when looking at the whole design. In those flows this
+# step can eliminate vast quantities of debug logic — for MegaBoom it
+# has historically removed ~50% of the design.
+#
+# eliminate_dead_logic is a pure netlist transform: it does not need a
+# die area, bterm placement or routing layers, so it is safe to run
+# here. Other synthesis-looking transforms in floorplan.tcl
+# (repair_tie_fanout, replace_arith_modules, remove_buffers,
+# repair_timing_helper) DO depend on floorplan-stage context (bterm
+# locations from initialize_floorplan, routing-layer setup) and must
+# stay in floorplan.tcl — moving them here was tried in PR #4187 and
+# regressed setup TNS by 1.7-46x on I/O-heavy designs (asap7/aes-block,
+# asap7/jpeg_lvt, asap7/swerv_wrapper, nangate45/ariane133).
+log_cmd eliminate_dead_logic
+
 source_step_tcl POST SYNTH
 orfs_write_db $::env(RESULTS_DIR)/1_synth.odb
 # Canonicalize 1_synth.sdc. The original SDC_FILE provided by