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@VeriSnip

VeriSnip

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VeriSnip

VeriSnip is the brainchild of @PedroAntunes178, a passionate hardware design enthusiast. Founded to serve as a dedicated repository for Pedro's numerous hobby projects in the realm of hardware design, this organization showcases his creative endeavors and technical innovations. We invite you to join us on this journey of discovery, where hardware design meets creativity, and where every circuit tells a unique story. Explore our projects, gain insights, and be inspired by the ingenuity that defines VeriSnip.

Connect with us today and witness the fusion of technology and imagination that defines our organization.

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  1. VeriSnip-Tool VeriSnip-Tool Public

    My Verilog Template is a project that I will be working on my free time. The project aim is to compile and elaborate Verilog modules. The Verilog cores are written in traditional Verilog and might …

    Python 1

  2. Open-Library Open-Library Public

    Python

  3. Blink-Core Blink-Core Public

    Verilog

  4. Utils-Tool Utils-Tool Public

    Repository containing Verilog simulators scripts.

    Makefile

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