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[WIP]

MRV-Core

MRV is a Multicycle RISC-V processor based on the desciption of such processor in the "Digital Design and Computer Architecture, RISC-V Edition" book from Sarah Harris and David Harris. The purpose of this core is both didactical and to serve as a light weight controller in other projects.

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This Repository exists because in my spar time I would like to start building a RISC-V CPU core.

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